| /drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| D | gmc_8_2_enum.h | 959 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| D | gmc_8_1_enum.h | 1089 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| /drivers/gpu/drm/amd/include/asic_reg/bif/ |
| D | bif_5_1_enum.h | 959 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| D | bif_5_0_enum.h | 1089 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| /drivers/gpu/drm/amd/include/asic_reg/smu/ |
| D | smu_8_0_enum.h | 959 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| D | smu_7_1_0_enum.h | 1118 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| D | smu_7_1_1_enum.h | 1119 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| D | smu_7_1_2_enum.h | 1137 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| D | smu_7_1_3_enum.h | 1173 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| /drivers/gpu/drm/amd/include/asic_reg/dce/ |
| D | dce_8_0_enum.h | 1044 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| D | dce_10_0_enum.h | 1664 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| /drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| D | uvd_6_0_enum.h | 972 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| D | uvd_5_0_enum.h | 1102 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v8_0.c | 2260 mod2array[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2288 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2292 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2856 mod2array[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
2861 mod2array[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3241 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3245 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3417 mod2array[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
3421 mod2array[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v8_0_tiling_mode_table_init()
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| D | gfx_v7_0.c | 1184 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
1188 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
1545 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
1549 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v7_0_tiling_mode_table_init()
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| D | gfx_v6_0.c | 593 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v6_0_tiling_mode_table_init()
833 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in gfx_v6_0_tiling_mode_table_init()
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| /drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_2_4_enum.h | 1254 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| D | oss_3_0_1_enum.h | 1355 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| D | oss_3_0_enum.h | 1388 ADDR_SURF_BANK_WIDTH_2 = 0x1, enumerator
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| /drivers/gpu/drm/radeon/ |
| D | sid.h | 1208 # define ADDR_SURF_BANK_WIDTH_2 1 macro
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| D | cik.c | 2860 macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
2864 macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
2975 macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
2979 macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3011 macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3015 macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
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| D | cikd.h | 1264 # define ADDR_SURF_BANK_WIDTH_2 1 macro
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| D | evergreend.h | 2219 # define ADDR_SURF_BANK_WIDTH_2 1 macro
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| D | si.c | 2679 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in si_tiling_mode_table_init()
2894 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in si_tiling_mode_table_init()
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| /drivers/gpu/drm/amd/include/asic_reg/si/ |
| D | sid.h | 1206 # define ADDR_SURF_BANK_WIDTH_2 1 macro
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