1 #ifndef _ADE7753_H 2 #define _ADE7753_H 3 4 #define ADE7753_WAVEFORM 0x01 5 #define ADE7753_AENERGY 0x02 6 #define ADE7753_RAENERGY 0x03 7 #define ADE7753_LAENERGY 0x04 8 #define ADE7753_VAENERGY 0x05 9 #define ADE7753_RVAENERGY 0x06 10 #define ADE7753_LVAENERGY 0x07 11 #define ADE7753_LVARENERGY 0x08 12 #define ADE7753_MODE 0x09 13 #define ADE7753_IRQEN 0x0A 14 #define ADE7753_STATUS 0x0B 15 #define ADE7753_RSTSTATUS 0x0C 16 #define ADE7753_CH1OS 0x0D 17 #define ADE7753_CH2OS 0x0E 18 #define ADE7753_GAIN 0x0F 19 #define ADE7753_PHCAL 0x10 20 #define ADE7753_APOS 0x11 21 #define ADE7753_WGAIN 0x12 22 #define ADE7753_WDIV 0x13 23 #define ADE7753_CFNUM 0x14 24 #define ADE7753_CFDEN 0x15 25 #define ADE7753_IRMS 0x16 26 #define ADE7753_VRMS 0x17 27 #define ADE7753_IRMSOS 0x18 28 #define ADE7753_VRMSOS 0x19 29 #define ADE7753_VAGAIN 0x1A 30 #define ADE7753_VADIV 0x1B 31 #define ADE7753_LINECYC 0x1C 32 #define ADE7753_ZXTOUT 0x1D 33 #define ADE7753_SAGCYC 0x1E 34 #define ADE7753_SAGLVL 0x1F 35 #define ADE7753_IPKLVL 0x20 36 #define ADE7753_VPKLVL 0x21 37 #define ADE7753_IPEAK 0x22 38 #define ADE7753_RSTIPEAK 0x23 39 #define ADE7753_VPEAK 0x24 40 #define ADE7753_RSTVPEAK 0x25 41 #define ADE7753_TEMP 0x26 42 #define ADE7753_PERIOD 0x27 43 #define ADE7753_TMODE 0x3D 44 #define ADE7753_CHKSUM 0x3E 45 #define ADE7753_DIEREV 0x3F 46 47 #define ADE7753_READ_REG(a) a 48 #define ADE7753_WRITE_REG(a) ((a) | 0x80) 49 50 #define ADE7753_MAX_TX 4 51 #define ADE7753_MAX_RX 4 52 #define ADE7753_STARTUP_DELAY 1 53 54 #define ADE7753_SPI_SLOW (u32)(300 * 1000) 55 #define ADE7753_SPI_BURST (u32)(1000 * 1000) 56 #define ADE7753_SPI_FAST (u32)(2000 * 1000) 57 58 /** 59 * struct ade7753_state - device instance specific data 60 * @us: actual spi_device 61 * @tx: transmit buffer 62 * @rx: receive buffer 63 * @buf_lock: mutex to protect tx and rx 64 **/ 65 struct ade7753_state { 66 struct spi_device *us; 67 struct mutex buf_lock; 68 u8 tx[ADE7753_MAX_TX] ____cacheline_aligned; 69 u8 rx[ADE7753_MAX_RX]; 70 }; 71 72 #endif 73