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Searched refs:ARRAY_2D_TILED_THIN1 (Results 1 – 25 of 37) sorted by relevance

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/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c408 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
418 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
428 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
438 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
458 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
468 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
478 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
508 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
518 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
528 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v6_0_tiling_mode_table_init()
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Dgfx_v8_0.c2149 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2153 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2157 modearray[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2161 modearray[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2165 modearray[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2183 modearray[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2195 modearray[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2243 modearray[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2320 modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
2324 modearray[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v8_0_tiling_mode_table_init()
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Dgfx_v7_0.c1053 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1057 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1061 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1065 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1069 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1086 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1098 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1146 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1220 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
1224 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in gfx_v7_0_tiling_mode_table_init()
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/drivers/gpu/drm/radeon/
Dsi.c2512 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2521 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2530 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2539 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2557 tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2566 tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2575 tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2602 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2611 tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
2620 tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in si_tiling_mode_table_init()
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Dcik.c2385 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2389 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2393 tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2397 tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2401 tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2421 tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2436 tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2451 tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2528 tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2532 tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
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Devergreen_cs.c95 return ARRAY_2D_TILED_THIN1; in evergreen_cs_get_aray_mode()
310 case ARRAY_2D_TILED_THIN1: in evergreen_surface_check()
325 case ARRAY_2D_TILED_THIN1: in evergreen_surface_value_conv_check()
882 case ARRAY_2D_TILED_THIN1: in evergreen_cs_track_validate_texture()
Dsid.h1184 # define ARRAY_2D_TILED_THIN1 4 macro
Dcikd.h1224 # define ARRAY_2D_TILED_THIN1 4 macro
/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_8_2_enum.h528 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Dgmc_8_1_enum.h38 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_5_1_enum.h528 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Dbif_5_0_enum.h38 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_8_0_enum.h528 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Dsmu_7_1_0_enum.h81 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Dsmu_7_1_1_enum.h88 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Dsmu_7_1_2_enum.h88 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Dsmu_7_1_3_enum.h85 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_enum.h38 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Ddce_10_0_enum.h613 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_enum.h541 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Duvd_5_0_enum.h51 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_enum.h223 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Doss_3_0_1_enum.h924 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
Doss_3_0_enum.h337 ARRAY_2D_TILED_THIN1 = 0x4, enumerator
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h1182 # define ARRAY_2D_TILED_THIN1 4 macro

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