Home
last modified time | relevance | path

Searched refs:AST_IO_CRTC_PORT (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/ast/
Dast_mode.c203 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4)); in ast_get_vbios_mode_info()
204 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); in ast_get_vbios_mode_info()
205 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); in ast_get_vbios_mode_info()
207 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); in ast_get_vbios_mode_info()
209 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); in ast_get_vbios_mode_info()
210 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, crtc->primary->fb->bits_per_pixel); in ast_get_vbios_mode_info()
211 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); in ast_get_vbios_mode_info()
212 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); in ast_get_vbios_mode_info()
213 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); in ast_get_vbios_mode_info()
215 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); in ast_get_vbios_mode_info()
[all …]
Dast_dp501.c22 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_ack()
24 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_ack()
30 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_nack()
32 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_nack()
40 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); in wait_ack()
56 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); in wait_nack()
69 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40); in set_cmd_trigger()
74 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00); in clear_cmd_trigger()
83 waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
101 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data); in ast_write_cmd()
[all …]
Dast_main.c93 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_detect_config_mode()
94 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); in ast_detect_config_mode()
188 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_detect_chip()
217 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff); in ast_detect_chip()
228 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); in ast_detect_chip()
434 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff); in ast_get_vram_info()
442 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff); in ast_get_vram_info()
Dast_post.c48 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04); in ast_enable_mmio()
79 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); in ast_set_def_ext_reg()
91 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info); in ast_set_def_ext_reg()
100 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01); in ast_set_def_ext_reg()
101 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00); in ast_set_def_ext_reg()
107 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); in ast_set_def_ext_reg()
278 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_init_dram_reg()
360 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_init_dram_reg()
387 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */ in ast_post_gpu()
1615 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_init_dram_2300()
[all …]
Dast_drv.h141 #define AST_IO_CRTC_PORT (0x54) macro
204 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8); in ast_open_key()