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Searched refs:CL (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dsddr3.c71 int CWL, CL, WR, DLL = 0, ODT = 0; in nvkm_sddr3_calc() local
82 CL = ram->next->bios.timing_10_CL; in nvkm_sddr3_calc()
88 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; in nvkm_sddr3_calc()
100 CL = ramxlat(ramddr3_cl, CL); in nvkm_sddr3_calc()
102 if (CL < 0 || CWL < 0 || WR < 0) in nvkm_sddr3_calc()
107 ram->mr[0] |= (CL & 0x0e) << 3; in nvkm_sddr3_calc()
108 ram->mr[0] |= (CL & 0x01) << 2; in nvkm_sddr3_calc()
Dgddr3.c73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; in nvkm_gddr3_calc() local
78 CL = ram->next->bios.timing_10_CL; in nvkm_gddr3_calc()
86 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; in nvkm_gddr3_calc()
102 CL = ramxlat(hi ? ramgddr3_cl_hi : ramgddr3_cl_lo, CL); in nvkm_gddr3_calc()
104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0) in nvkm_gddr3_calc()
109 ram->mr[0] |= (CL & 0x07) << 4; in nvkm_gddr3_calc()
110 ram->mr[0] |= (CL & 0x08) >> 1; in nvkm_gddr3_calc()
Dsddr2.c62 int CL, WR, DLL = 0, ODT = 0; in nvkm_sddr2_calc() local
66 CL = ram->next->bios.timing_10_CL; in nvkm_sddr2_calc()
72 CL = (ram->next->bios.timing[1] & 0x0000001f); in nvkm_sddr2_calc()
85 CL = ramxlat(ramddr2_cl, CL); in nvkm_sddr2_calc()
87 if (CL < 0 || WR < 0) in nvkm_sddr2_calc()
92 ram->mr[0] |= (CL & 0x07) << 4; in nvkm_sddr2_calc()
Dgddr5.c38 int WL, CL, WR, at[2], dt, ds; in nvkm_gddr5_calc() local
59 CL = (ram->next->bios.timing[1] & 0x0000001f); in nvkm_gddr5_calc()
70 if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35) in nvkm_gddr5_calc()
72 CL -= 5; in nvkm_gddr5_calc()
77 ram->mr[0] |= (CL & 0x0f) << 3; in nvkm_gddr5_calc()
119 ram->mr[8] |= (CL & 0x10) >> 4; in nvkm_gddr5_calc()
Dramnv50.c88 T(CWL) = T(CL) - 1; in nv50_ram_timing_calc()
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
101 (0x2f + T(CL) - T(CWL)); in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
106 (0x2e + T(CL) - T(CWL)); in nv50_ram_timing_calc()
113 (3 + T(CL) - T(CWL)); in nv50_ram_timing_calc()
118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | in nv50_ram_timing_calc()
120 (T(CL) - 1) << 8 | in nv50_ram_timing_calc()
121 (T(CL) - 1); in nv50_ram_timing_calc()
129 timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16; in nv50_ram_timing_calc()
[all …]
Dramgt215.c364 T(CWL) = T(CL) - 1; in gt215_ram_timing_calc()
378 (5 + T(CL) - T(CWL)); in gt215_ram_timing_calc()
384 (0x30 + T(CL)) << 24 | in gt215_ram_timing_calc()
385 (0xb + T(CL)) << 8 | in gt215_ram_timing_calc()
386 (T(CL) - 1); in gt215_ram_timing_calc()
393 max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 | in gt215_ram_timing_calc()
395 timing[6] = (0x5a + T(CL)) << 16 | in gt215_ram_timing_calc()
396 max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 | in gt215_ram_timing_calc()
397 (0x50 + T(CL) - T(CWL)); in gt215_ram_timing_calc()
399 ((tUNK_base + T(CL)) << 16) | in gt215_ram_timing_calc()
[all …]
/drivers/video/fbdev/aty/
Daty128fb.c313 u8 CL; member
328 .CL = 3,
342 .CL = 3,
356 .CL = 2,
370 .CL = 3,
1456 m->CL + in aty128_ddafifo()
/drivers/isdn/hardware/eicon/
Dpc.h275 #define CL 0xb0 /* congestion level */ macro