1 /*
2 * AMD Cryptographic Coprocessor (CCP) driver
3 *
4 * Copyright (C) 2013,2016 Advanced Micro Devices, Inc.
5 *
6 * Author: Tom Lendacky <thomas.lendacky@amd.com>
7 * Author: Gary R Hook <gary.hook@amd.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #ifndef __CCP_DEV_H__
15 #define __CCP_DEV_H__
16
17 #include <linux/device.h>
18 #include <linux/pci.h>
19 #include <linux/spinlock.h>
20 #include <linux/mutex.h>
21 #include <linux/list.h>
22 #include <linux/wait.h>
23 #include <linux/dmapool.h>
24 #include <linux/hw_random.h>
25 #include <linux/bitops.h>
26 #include <linux/interrupt.h>
27 #include <linux/irqreturn.h>
28 #include <linux/dmaengine.h>
29
30 #define MAX_CCP_NAME_LEN 16
31 #define MAX_DMAPOOL_NAME_LEN 32
32
33 #define MAX_HW_QUEUES 5
34 #define MAX_CMD_QLEN 100
35
36 #define TRNG_RETRIES 10
37
38 #define CACHE_NONE 0x00
39 #define CACHE_WB_NO_ALLOC 0xb7
40
41 /****** Register Mappings ******/
42 #define Q_MASK_REG 0x000
43 #define TRNG_OUT_REG 0x00c
44 #define IRQ_MASK_REG 0x040
45 #define IRQ_STATUS_REG 0x200
46
47 #define DEL_CMD_Q_JOB 0x124
48 #define DEL_Q_ACTIVE 0x00000200
49 #define DEL_Q_ID_SHIFT 6
50
51 #define CMD_REQ0 0x180
52 #define CMD_REQ_INCR 0x04
53
54 #define CMD_Q_STATUS_BASE 0x210
55 #define CMD_Q_INT_STATUS_BASE 0x214
56 #define CMD_Q_STATUS_INCR 0x20
57
58 #define CMD_Q_CACHE_BASE 0x228
59 #define CMD_Q_CACHE_INC 0x20
60
61 #define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f)
62 #define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f)
63
64 /* ------------------------ CCP Version 5 Specifics ------------------------ */
65 #define CMD5_QUEUE_MASK_OFFSET 0x00
66 #define CMD5_QUEUE_PRIO_OFFSET 0x04
67 #define CMD5_REQID_CONFIG_OFFSET 0x08
68 #define CMD5_CMD_TIMEOUT_OFFSET 0x10
69 #define LSB_PUBLIC_MASK_LO_OFFSET 0x18
70 #define LSB_PUBLIC_MASK_HI_OFFSET 0x1C
71 #define LSB_PRIVATE_MASK_LO_OFFSET 0x20
72 #define LSB_PRIVATE_MASK_HI_OFFSET 0x24
73
74 #define CMD5_Q_CONTROL_BASE 0x0000
75 #define CMD5_Q_TAIL_LO_BASE 0x0004
76 #define CMD5_Q_HEAD_LO_BASE 0x0008
77 #define CMD5_Q_INT_ENABLE_BASE 0x000C
78 #define CMD5_Q_INTERRUPT_STATUS_BASE 0x0010
79
80 #define CMD5_Q_STATUS_BASE 0x0100
81 #define CMD5_Q_INT_STATUS_BASE 0x0104
82 #define CMD5_Q_DMA_STATUS_BASE 0x0108
83 #define CMD5_Q_DMA_READ_STATUS_BASE 0x010C
84 #define CMD5_Q_DMA_WRITE_STATUS_BASE 0x0110
85 #define CMD5_Q_ABORT_BASE 0x0114
86 #define CMD5_Q_AX_CACHE_BASE 0x0118
87
88 #define CMD5_CONFIG_0_OFFSET 0x6000
89 #define CMD5_TRNG_CTL_OFFSET 0x6008
90 #define CMD5_AES_MASK_OFFSET 0x6010
91 #define CMD5_CLK_GATE_CTL_OFFSET 0x603C
92
93 /* Address offset between two virtual queue registers */
94 #define CMD5_Q_STATUS_INCR 0x1000
95
96 /* Bit masks */
97 #define CMD5_Q_RUN 0x1
98 #define CMD5_Q_HALT 0x2
99 #define CMD5_Q_MEM_LOCATION 0x4
100 #define CMD5_Q_SIZE 0x1F
101 #define CMD5_Q_SHIFT 3
102 #define COMMANDS_PER_QUEUE 16
103 #define QUEUE_SIZE_VAL ((ffs(COMMANDS_PER_QUEUE) - 2) & \
104 CMD5_Q_SIZE)
105 #define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
106 #define Q_DESC_SIZE sizeof(struct ccp5_desc)
107 #define Q_SIZE(n) (COMMANDS_PER_QUEUE*(n))
108
109 #define INT_COMPLETION 0x1
110 #define INT_ERROR 0x2
111 #define INT_QUEUE_STOPPED 0x4
112 #define INT_EMPTY_QUEUE 0x8
113 #define SUPPORTED_INTERRUPTS (INT_COMPLETION | INT_ERROR)
114
115 #define LSB_REGION_WIDTH 5
116 #define MAX_LSB_CNT 8
117
118 #define LSB_SIZE 16
119 #define LSB_ITEM_SIZE 32
120 #define PLSB_MAP_SIZE (LSB_SIZE)
121 #define SLSB_MAP_SIZE (MAX_LSB_CNT * LSB_SIZE)
122
123 #define LSB_ENTRY_NUMBER(LSB_ADDR) (LSB_ADDR / LSB_ITEM_SIZE)
124
125 /* ------------------------ CCP Version 3 Specifics ------------------------ */
126 #define REQ0_WAIT_FOR_WRITE 0x00000004
127 #define REQ0_INT_ON_COMPLETE 0x00000002
128 #define REQ0_STOP_ON_COMPLETE 0x00000001
129
130 #define REQ0_CMD_Q_SHIFT 9
131 #define REQ0_JOBID_SHIFT 3
132
133 /****** REQ1 Related Values ******/
134 #define REQ1_PROTECT_SHIFT 27
135 #define REQ1_ENGINE_SHIFT 23
136 #define REQ1_KEY_KSB_SHIFT 2
137
138 #define REQ1_EOM 0x00000002
139 #define REQ1_INIT 0x00000001
140
141 /* AES Related Values */
142 #define REQ1_AES_TYPE_SHIFT 21
143 #define REQ1_AES_MODE_SHIFT 18
144 #define REQ1_AES_ACTION_SHIFT 17
145 #define REQ1_AES_CFB_SIZE_SHIFT 10
146
147 /* XTS-AES Related Values */
148 #define REQ1_XTS_AES_SIZE_SHIFT 10
149
150 /* SHA Related Values */
151 #define REQ1_SHA_TYPE_SHIFT 21
152
153 /* RSA Related Values */
154 #define REQ1_RSA_MOD_SIZE_SHIFT 10
155
156 /* Pass-Through Related Values */
157 #define REQ1_PT_BW_SHIFT 12
158 #define REQ1_PT_BS_SHIFT 10
159
160 /* ECC Related Values */
161 #define REQ1_ECC_AFFINE_CONVERT 0x00200000
162 #define REQ1_ECC_FUNCTION_SHIFT 18
163
164 /****** REQ4 Related Values ******/
165 #define REQ4_KSB_SHIFT 18
166 #define REQ4_MEMTYPE_SHIFT 16
167
168 /****** REQ6 Related Values ******/
169 #define REQ6_MEMTYPE_SHIFT 16
170
171 /****** Key Storage Block ******/
172 #define KSB_START 77
173 #define KSB_END 127
174 #define KSB_COUNT (KSB_END - KSB_START + 1)
175 #define CCP_SB_BITS 256
176
177 #define CCP_JOBID_MASK 0x0000003f
178
179 /* ------------------------ General CCP Defines ------------------------ */
180
181 #define CCP_DMAPOOL_MAX_SIZE 64
182 #define CCP_DMAPOOL_ALIGN BIT(5)
183
184 #define CCP_REVERSE_BUF_SIZE 64
185
186 #define CCP_AES_KEY_SB_COUNT 1
187 #define CCP_AES_CTX_SB_COUNT 1
188
189 #define CCP_XTS_AES_KEY_SB_COUNT 1
190 #define CCP5_XTS_AES_KEY_SB_COUNT 2
191 #define CCP_XTS_AES_CTX_SB_COUNT 1
192
193 #define CCP_SHA_SB_COUNT 1
194
195 #define CCP_RSA_MAX_WIDTH 4096
196
197 #define CCP_PASSTHRU_BLOCKSIZE 256
198 #define CCP_PASSTHRU_MASKSIZE 32
199 #define CCP_PASSTHRU_SB_COUNT 1
200
201 #define CCP_ECC_MODULUS_BYTES 48 /* 384-bits */
202 #define CCP_ECC_MAX_OPERANDS 6
203 #define CCP_ECC_MAX_OUTPUTS 3
204 #define CCP_ECC_SRC_BUF_SIZE 448
205 #define CCP_ECC_DST_BUF_SIZE 192
206 #define CCP_ECC_OPERAND_SIZE 64
207 #define CCP_ECC_OUTPUT_SIZE 64
208 #define CCP_ECC_RESULT_OFFSET 60
209 #define CCP_ECC_RESULT_SUCCESS 0x0001
210
211 #define CCP_SB_BYTES 32
212
213 struct ccp_op;
214 struct ccp_device;
215 struct ccp_cmd;
216 struct ccp_fns;
217
218 struct ccp_dma_cmd {
219 struct list_head entry;
220
221 struct ccp_cmd ccp_cmd;
222 };
223
224 struct ccp_dma_desc {
225 struct list_head entry;
226
227 struct ccp_device *ccp;
228
229 struct list_head pending;
230 struct list_head active;
231
232 enum dma_status status;
233 struct dma_async_tx_descriptor tx_desc;
234 size_t len;
235 };
236
237 struct ccp_dma_chan {
238 struct ccp_device *ccp;
239
240 spinlock_t lock;
241 struct list_head created;
242 struct list_head pending;
243 struct list_head active;
244 struct list_head complete;
245
246 struct tasklet_struct cleanup_tasklet;
247
248 enum dma_status status;
249 struct dma_chan dma_chan;
250 };
251
252 struct ccp_cmd_queue {
253 struct ccp_device *ccp;
254
255 /* Queue identifier */
256 u32 id;
257
258 /* Queue dma pool */
259 struct dma_pool *dma_pool;
260
261 /* Queue base address (not neccessarily aligned)*/
262 struct ccp5_desc *qbase;
263
264 /* Aligned queue start address (per requirement) */
265 struct mutex q_mutex ____cacheline_aligned;
266 unsigned int qidx;
267
268 /* Version 5 has different requirements for queue memory */
269 unsigned int qsize;
270 dma_addr_t qbase_dma;
271 dma_addr_t qdma_tail;
272
273 /* Per-queue reserved storage block(s) */
274 u32 sb_key;
275 u32 sb_ctx;
276
277 /* Bitmap of LSBs that can be accessed by this queue */
278 DECLARE_BITMAP(lsbmask, MAX_LSB_CNT);
279 /* Private LSB that is assigned to this queue, or -1 if none.
280 * Bitmap for my private LSB, unused otherwise
281 */
282 unsigned int lsb;
283 DECLARE_BITMAP(lsbmap, PLSB_MAP_SIZE);
284
285 /* Queue processing thread */
286 struct task_struct *kthread;
287 unsigned int active;
288 unsigned int suspended;
289
290 /* Number of free command slots available */
291 unsigned int free_slots;
292
293 /* Interrupt masks */
294 u32 int_ok;
295 u32 int_err;
296
297 /* Register addresses for queue */
298 void __iomem *reg_control;
299 void __iomem *reg_tail_lo;
300 void __iomem *reg_head_lo;
301 void __iomem *reg_int_enable;
302 void __iomem *reg_interrupt_status;
303 void __iomem *reg_status;
304 void __iomem *reg_int_status;
305 void __iomem *reg_dma_status;
306 void __iomem *reg_dma_read_status;
307 void __iomem *reg_dma_write_status;
308 u32 qcontrol; /* Cached control register */
309
310 /* Status values from job */
311 u32 int_status;
312 u32 q_status;
313 u32 q_int_status;
314 u32 cmd_error;
315
316 /* Interrupt wait queue */
317 wait_queue_head_t int_queue;
318 unsigned int int_rcvd;
319 } ____cacheline_aligned;
320
321 struct ccp_device {
322 struct list_head entry;
323
324 struct ccp_vdata *vdata;
325 unsigned int ord;
326 char name[MAX_CCP_NAME_LEN];
327 char rngname[MAX_CCP_NAME_LEN];
328
329 struct device *dev;
330
331 /* Bus specific device information
332 */
333 void *dev_specific;
334 int (*get_irq)(struct ccp_device *ccp);
335 void (*free_irq)(struct ccp_device *ccp);
336 unsigned int qim;
337 unsigned int irq;
338 bool use_tasklet;
339 struct tasklet_struct irq_tasklet;
340
341 /* I/O area used for device communication. The register mapping
342 * starts at an offset into the mapped bar.
343 * The CMD_REQx registers and the Delete_Cmd_Queue_Job register
344 * need to be protected while a command queue thread is accessing
345 * them.
346 */
347 struct mutex req_mutex ____cacheline_aligned;
348 void __iomem *io_map;
349 void __iomem *io_regs;
350
351 /* Master lists that all cmds are queued on. Because there can be
352 * more than one CCP command queue that can process a cmd a separate
353 * backlog list is neeeded so that the backlog completion call
354 * completes before the cmd is available for execution.
355 */
356 spinlock_t cmd_lock ____cacheline_aligned;
357 unsigned int cmd_count;
358 struct list_head cmd;
359 struct list_head backlog;
360
361 /* The command queues. These represent the queues available on the
362 * CCP that are available for processing cmds
363 */
364 struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
365 unsigned int cmd_q_count;
366
367 /* Support for the CCP True RNG
368 */
369 struct hwrng hwrng;
370 unsigned int hwrng_retries;
371
372 /* Support for the CCP DMA capabilities
373 */
374 struct dma_device dma_dev;
375 struct ccp_dma_chan *ccp_dma_chan;
376 struct kmem_cache *dma_cmd_cache;
377 struct kmem_cache *dma_desc_cache;
378
379 /* A counter used to generate job-ids for cmds submitted to the CCP
380 */
381 atomic_t current_id ____cacheline_aligned;
382
383 /* The v3 CCP uses key storage blocks (SB) to maintain context for
384 * certain operations. To prevent multiple cmds from using the same
385 * SB range a command queue reserves an SB range for the duration of
386 * the cmd. Each queue, will however, reserve 2 SB blocks for
387 * operations that only require single SB entries (eg. AES context/iv
388 * and key) in order to avoid allocation contention. This will reserve
389 * at most 10 SB entries, leaving 40 SB entries available for dynamic
390 * allocation.
391 *
392 * The v5 CCP Local Storage Block (LSB) is broken up into 8
393 * memrory ranges, each of which can be enabled for access by one
394 * or more queues. Device initialization takes this into account,
395 * and attempts to assign one region for exclusive use by each
396 * available queue; the rest are then aggregated as "public" use.
397 * If there are fewer regions than queues, all regions are shared
398 * amongst all queues.
399 */
400 struct mutex sb_mutex ____cacheline_aligned;
401 DECLARE_BITMAP(sb, KSB_COUNT);
402 wait_queue_head_t sb_queue;
403 unsigned int sb_avail;
404 unsigned int sb_count;
405 u32 sb_start;
406
407 /* Bitmap of shared LSBs, if any */
408 DECLARE_BITMAP(lsbmap, SLSB_MAP_SIZE);
409
410 /* Suspend support */
411 unsigned int suspending;
412 wait_queue_head_t suspend_queue;
413
414 /* DMA caching attribute support */
415 unsigned int axcache;
416 };
417
418 enum ccp_memtype {
419 CCP_MEMTYPE_SYSTEM = 0,
420 CCP_MEMTYPE_SB,
421 CCP_MEMTYPE_LOCAL,
422 CCP_MEMTYPE__LAST,
423 };
424 #define CCP_MEMTYPE_LSB CCP_MEMTYPE_KSB
425
426 struct ccp_dma_info {
427 dma_addr_t address;
428 unsigned int offset;
429 unsigned int length;
430 enum dma_data_direction dir;
431 };
432
433 struct ccp_dm_workarea {
434 struct device *dev;
435 struct dma_pool *dma_pool;
436 unsigned int length;
437
438 u8 *address;
439 struct ccp_dma_info dma;
440 };
441
442 struct ccp_sg_workarea {
443 struct scatterlist *sg;
444 int nents;
445
446 struct scatterlist *dma_sg;
447 struct device *dma_dev;
448 unsigned int dma_count;
449 enum dma_data_direction dma_dir;
450
451 unsigned int sg_used;
452
453 u64 bytes_left;
454 };
455
456 struct ccp_data {
457 struct ccp_sg_workarea sg_wa;
458 struct ccp_dm_workarea dm_wa;
459 };
460
461 struct ccp_mem {
462 enum ccp_memtype type;
463 union {
464 struct ccp_dma_info dma;
465 u32 sb;
466 } u;
467 };
468
469 struct ccp_aes_op {
470 enum ccp_aes_type type;
471 enum ccp_aes_mode mode;
472 enum ccp_aes_action action;
473 unsigned int size;
474 };
475
476 struct ccp_xts_aes_op {
477 enum ccp_aes_type type;
478 enum ccp_aes_action action;
479 enum ccp_xts_aes_unit_size unit_size;
480 };
481
482 struct ccp_sha_op {
483 enum ccp_sha_type type;
484 u64 msg_bits;
485 };
486
487 struct ccp_rsa_op {
488 u32 mod_size;
489 u32 input_len;
490 };
491
492 struct ccp_passthru_op {
493 enum ccp_passthru_bitwise bit_mod;
494 enum ccp_passthru_byteswap byte_swap;
495 };
496
497 struct ccp_ecc_op {
498 enum ccp_ecc_function function;
499 };
500
501 struct ccp_op {
502 struct ccp_cmd_queue *cmd_q;
503
504 u32 jobid;
505 u32 ioc;
506 u32 soc;
507 u32 sb_key;
508 u32 sb_ctx;
509 u32 init;
510 u32 eom;
511
512 struct ccp_mem src;
513 struct ccp_mem dst;
514 struct ccp_mem exp;
515
516 union {
517 struct ccp_aes_op aes;
518 struct ccp_xts_aes_op xts;
519 struct ccp_sha_op sha;
520 struct ccp_rsa_op rsa;
521 struct ccp_passthru_op passthru;
522 struct ccp_ecc_op ecc;
523 } u;
524 struct ccp_mem key;
525 };
526
ccp_addr_lo(struct ccp_dma_info * info)527 static inline u32 ccp_addr_lo(struct ccp_dma_info *info)
528 {
529 return lower_32_bits(info->address + info->offset);
530 }
531
ccp_addr_hi(struct ccp_dma_info * info)532 static inline u32 ccp_addr_hi(struct ccp_dma_info *info)
533 {
534 return upper_32_bits(info->address + info->offset) & 0x0000ffff;
535 }
536
537 /**
538 * descriptor for version 5 CPP commands
539 * 8 32-bit words:
540 * word 0: function; engine; control bits
541 * word 1: length of source data
542 * word 2: low 32 bits of source pointer
543 * word 3: upper 16 bits of source pointer; source memory type
544 * word 4: low 32 bits of destination pointer
545 * word 5: upper 16 bits of destination pointer; destination memory type
546 * word 6: low 32 bits of key pointer
547 * word 7: upper 16 bits of key pointer; key memory type
548 */
549 struct dword0 {
550 __le32 soc:1;
551 __le32 ioc:1;
552 __le32 rsvd1:1;
553 __le32 init:1;
554 __le32 eom:1; /* AES/SHA only */
555 __le32 function:15;
556 __le32 engine:4;
557 __le32 prot:1;
558 __le32 rsvd2:7;
559 };
560
561 struct dword3 {
562 __le32 src_hi:16;
563 __le32 src_mem:2;
564 __le32 lsb_cxt_id:8;
565 __le32 rsvd1:5;
566 __le32 fixed:1;
567 };
568
569 union dword4 {
570 __le32 dst_lo; /* NON-SHA */
571 __le32 sha_len_lo; /* SHA */
572 };
573
574 union dword5 {
575 struct {
576 __le32 dst_hi:16;
577 __le32 dst_mem:2;
578 __le32 rsvd1:13;
579 __le32 fixed:1;
580 } fields;
581 __le32 sha_len_hi;
582 };
583
584 struct dword7 {
585 __le32 key_hi:16;
586 __le32 key_mem:2;
587 __le32 rsvd1:14;
588 };
589
590 struct ccp5_desc {
591 struct dword0 dw0;
592 __le32 length;
593 __le32 src_lo;
594 struct dword3 dw3;
595 union dword4 dw4;
596 union dword5 dw5;
597 __le32 key_lo;
598 struct dword7 dw7;
599 };
600
601 int ccp_pci_init(void);
602 void ccp_pci_exit(void);
603
604 int ccp_platform_init(void);
605 void ccp_platform_exit(void);
606
607 void ccp_add_device(struct ccp_device *ccp);
608 void ccp_del_device(struct ccp_device *ccp);
609
610 extern void ccp_log_error(struct ccp_device *, int);
611
612 struct ccp_device *ccp_alloc_struct(struct device *dev);
613 bool ccp_queues_suspended(struct ccp_device *ccp);
614 int ccp_cmd_queue_thread(void *data);
615 int ccp_trng_read(struct hwrng *rng, void *data, size_t max, bool wait);
616
617 int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd);
618
619 int ccp_register_rng(struct ccp_device *ccp);
620 void ccp_unregister_rng(struct ccp_device *ccp);
621 int ccp_dmaengine_register(struct ccp_device *ccp);
622 void ccp_dmaengine_unregister(struct ccp_device *ccp);
623
624 /* Structure for computation functions that are device-specific */
625 struct ccp_actions {
626 int (*aes)(struct ccp_op *);
627 int (*xts_aes)(struct ccp_op *);
628 int (*sha)(struct ccp_op *);
629 int (*rsa)(struct ccp_op *);
630 int (*passthru)(struct ccp_op *);
631 int (*ecc)(struct ccp_op *);
632 u32 (*sballoc)(struct ccp_cmd_queue *, unsigned int);
633 void (*sbfree)(struct ccp_cmd_queue *, unsigned int,
634 unsigned int);
635 unsigned int (*get_free_slots)(struct ccp_cmd_queue *);
636 int (*init)(struct ccp_device *);
637 void (*destroy)(struct ccp_device *);
638 irqreturn_t (*irqhandler)(int, void *);
639 };
640
641 /* Structure to hold CCP version-specific values */
642 struct ccp_vdata {
643 const unsigned int version;
644 void (*setup)(struct ccp_device *);
645 const struct ccp_actions *perform;
646 const unsigned int bar;
647 const unsigned int offset;
648 };
649
650 extern const struct ccp_vdata ccpv3;
651 extern const struct ccp_vdata ccpv5a;
652 extern const struct ccp_vdata ccpv5b;
653
654 #endif
655