Searched refs:CSR7 (Results 1 – 9 of 9) sorted by relevance
| /drivers/net/ethernet/dec/tulip/ |
| D | pnic.c | 62 iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkFail) | TPLnkPass, ioaddr + CSR7); in pnic_lnk_change()
83 iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkPass) | TPLnkFail, ioaddr + CSR7); in pnic_lnk_change()
94 if(!ioread32(ioaddr + CSR7)) { in pnic_timer()
162 if(!ioread32(ioaddr + CSR7)) { in pnic_timer()
168 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7); in pnic_timer()
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| D | xircom_cb.c | 55 #define CSR7 0x38 macro
872 val = xr32(CSR7); /* Interrupt enable register */ in enable_transmit_interrupt()
874 xw32(CSR7, val); in enable_transmit_interrupt()
888 val = xr32(CSR7); /* Interrupt enable register */ in enable_receive_interrupt()
890 xw32(CSR7, val); in enable_receive_interrupt()
903 val = xr32(CSR7); /* Interrupt enable register */ in enable_link_interrupt()
905 xw32(CSR7, val); in enable_link_interrupt()
919 xw32(CSR7, 0); in disable_all_interrupts()
932 val = xr32(CSR7); /* Interrupt enable register */ in enable_common_interrupts()
941 xw32(CSR7, val); in enable_common_interrupts()
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| D | interrupt.c | 323 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, tp->base_addr+CSR7); in tulip_poll()
554 iowrite32(tulip_tbl[tp->chip_id].valid_intrs&~RxPollInt, ioaddr + CSR7); in tulip_interrupt()
727 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7); in tulip_interrupt()
744 iowrite32(0x00, ioaddr + CSR7); in tulip_interrupt()
749 … iowrite32(((~csr5) & 0x0001ebef) | AbnormalIntr | TimerInt, ioaddr + CSR7); in tulip_interrupt()
787 iowrite32(0x00, ioaddr + CSR7);
796 ioaddr + CSR7);
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| D | tulip_core.c | 446 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7); in tulip_up()
492 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7); in tulip_up()
566 (int)ioread32(ioaddr + CSR7), in tulip_tx_timeout()
767 iowrite32 (0x00000000, ioaddr + CSR7); in tulip_down()
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| D | tulip.h | 113 CSR7 = 0x38, enumerator
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| /drivers/net/wireless/ralink/rt2x00/ |
| D | rt2400pci.c | 977 rt2x00mmio_register_read(rt2x00dev, CSR7, ®); in rt2400pci_toggle_irq()
978 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2400pci_toggle_irq()
1384 rt2x00mmio_register_read(rt2x00dev, CSR7, ®); in rt2400pci_interrupt()
1385 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2400pci_interrupt()
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| D | rt2400pci.h | 127 #define CSR7 0x001c macro
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| D | rt2500pci.c | 1131 rt2x00mmio_register_read(rt2x00dev, CSR7, ®); in rt2500pci_toggle_irq()
1132 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2500pci_toggle_irq()
1512 rt2x00mmio_register_read(rt2x00dev, CSR7, ®); in rt2500pci_interrupt()
1513 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2500pci_interrupt()
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| D | rt2500pci.h | 152 #define CSR7 0x001c macro
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