Searched refs:DC_HPD1_INT_CONTROL (Results 1 – 10 of 10) sorted by relevance
/drivers/gpu/drm/radeon/ |
D | evergreen.c | 1767 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_hpd_set_polarity() 1772 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_hpd_set_polarity() 4594 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state() 4595 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_disable_interrupt_state() 4632 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set() 4815 WREG32(DC_HPD1_INT_CONTROL, hpd1); in evergreen_irq_set() 4911 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_irq_ack() 4913 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_irq_ack() 4942 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_irq_ack() 4944 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_irq_ack()
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D | r600.c | 862 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_hpd_set_polarity() 867 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_hpd_set_polarity() 3636 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state() 3637 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_disable_interrupt_state() 3788 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set() 3884 WREG32(DC_HPD1_INT_CONTROL, hpd1); in r600_irq_set() 3955 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_irq_ack() 3957 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_irq_ack()
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D | si.c | 5984 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state() 5985 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_disable_interrupt_state() 6096 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in si_irq_set() 6234 WREG32(DC_HPD1_INT_CONTROL, hpd1); in si_irq_set() 6318 tmp = RREG32(DC_HPD1_INT_CONTROL); in si_irq_ack() 6320 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_irq_ack() 6349 tmp = RREG32(DC_HPD1_INT_CONTROL); in si_irq_ack() 6351 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_irq_ack()
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D | cik.c | 6981 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state() 6982 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_disable_interrupt_state() 7112 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set() 7266 WREG32(DC_HPD1_INT_CONTROL, hpd1); in cik_irq_set() 7367 tmp = RREG32(DC_HPD1_INT_CONTROL); in cik_irq_ack() 7369 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack() 7397 tmp = RREG32(DC_HPD1_INT_CONTROL); in cik_irq_ack() 7399 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
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D | sid.h | 880 #define DC_HPD1_INT_CONTROL 0x6020 macro
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D | cikd.h | 956 #define DC_HPD1_INT_CONTROL 0x6020 macro
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D | evergreend.h | 1346 #define DC_HPD1_INT_CONTROL 0x6020 macro
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D | r600d.h | 856 #define DC_HPD1_INT_CONTROL 0x7d04 macro
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/drivers/gpu/drm/amd/amdgpu/ |
D | dce_v6_0.c | 98 DC_HPD1_INT_CONTROL, 308 tmp = RREG32(DC_HPD1_INT_CONTROL); in dce_v6_0_hpd_set_polarity() 313 WREG32(DC_HPD1_INT_CONTROL, tmp); in dce_v6_0_hpd_set_polarity() 412 dc_hpd_int_cntl_reg = DC_HPD1_INT_CONTROL; in dce_v6_0_hpd_init() 2586 dc_hpd_int_cntl_reg = DC_HPD1_INT_CONTROL; in dce_v6_0_set_hpd_interrupt_state()
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/drivers/gpu/drm/amd/include/asic_reg/si/ |
D | sid.h | 884 #define DC_HPD1_INT_CONTROL 0x1808 macro
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