1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 #ifndef __QLA_DEF_H 8 #define __QLA_DEF_H 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/types.h> 13 #include <linux/module.h> 14 #include <linux/list.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/sched.h> 18 #include <linux/slab.h> 19 #include <linux/dmapool.h> 20 #include <linux/mempool.h> 21 #include <linux/spinlock.h> 22 #include <linux/completion.h> 23 #include <linux/interrupt.h> 24 #include <linux/workqueue.h> 25 #include <linux/firmware.h> 26 #include <linux/aer.h> 27 #include <linux/mutex.h> 28 29 #include <scsi/scsi.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_cmnd.h> 33 #include <scsi/scsi_transport_fc.h> 34 #include <scsi/scsi_bsg_fc.h> 35 36 #include "qla_bsg.h" 37 #include "qla_nx.h" 38 #include "qla_nx2.h" 39 #define QLA2XXX_DRIVER_NAME "qla2xxx" 40 #define QLA2XXX_APIDEV "ql2xapidev" 41 #define QLA2XXX_MANUFACTURER "QLogic Corporation" 42 43 /* 44 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places, 45 * but that's fine as we don't look at the last 24 ones for 46 * ISP2100 HBAs. 47 */ 48 #define MAILBOX_REGISTER_COUNT_2100 8 49 #define MAILBOX_REGISTER_COUNT_2200 24 50 #define MAILBOX_REGISTER_COUNT 32 51 52 #define QLA2200A_RISC_ROM_VER 4 53 #define FPM_2300 6 54 #define FPM_2310 7 55 56 #include "qla_settings.h" 57 58 /* 59 * Data bit definitions 60 */ 61 #define BIT_0 0x1 62 #define BIT_1 0x2 63 #define BIT_2 0x4 64 #define BIT_3 0x8 65 #define BIT_4 0x10 66 #define BIT_5 0x20 67 #define BIT_6 0x40 68 #define BIT_7 0x80 69 #define BIT_8 0x100 70 #define BIT_9 0x200 71 #define BIT_10 0x400 72 #define BIT_11 0x800 73 #define BIT_12 0x1000 74 #define BIT_13 0x2000 75 #define BIT_14 0x4000 76 #define BIT_15 0x8000 77 #define BIT_16 0x10000 78 #define BIT_17 0x20000 79 #define BIT_18 0x40000 80 #define BIT_19 0x80000 81 #define BIT_20 0x100000 82 #define BIT_21 0x200000 83 #define BIT_22 0x400000 84 #define BIT_23 0x800000 85 #define BIT_24 0x1000000 86 #define BIT_25 0x2000000 87 #define BIT_26 0x4000000 88 #define BIT_27 0x8000000 89 #define BIT_28 0x10000000 90 #define BIT_29 0x20000000 91 #define BIT_30 0x40000000 92 #define BIT_31 0x80000000 93 94 #define LSB(x) ((uint8_t)(x)) 95 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8)) 96 97 #define LSW(x) ((uint16_t)(x)) 98 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16)) 99 100 #define LSD(x) ((uint32_t)((uint64_t)(x))) 101 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 102 103 #define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y))) 104 105 /* 106 * I/O register 107 */ 108 109 #define RD_REG_BYTE(addr) readb(addr) 110 #define RD_REG_WORD(addr) readw(addr) 111 #define RD_REG_DWORD(addr) readl(addr) 112 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr) 113 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr) 114 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr) 115 #define WRT_REG_BYTE(addr, data) writeb(data,addr) 116 #define WRT_REG_WORD(addr, data) writew(data,addr) 117 #define WRT_REG_DWORD(addr, data) writel(data,addr) 118 119 /* 120 * ISP83XX specific remote register addresses 121 */ 122 #define QLA83XX_LED_PORT0 0x00201320 123 #define QLA83XX_LED_PORT1 0x00201328 124 #define QLA83XX_IDC_DEV_STATE 0x22102384 125 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380 126 #define QLA83XX_IDC_MINOR_VERSION 0x22102398 127 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388 128 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c 129 #define QLA83XX_IDC_CONTROL 0x22102390 130 #define QLA83XX_IDC_AUDIT 0x22102394 131 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c 132 #define QLA83XX_DRIVER_LOCKID 0x22102104 133 #define QLA83XX_DRIVER_LOCK 0x8111c028 134 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c 135 #define QLA83XX_FLASH_LOCKID 0x22102100 136 #define QLA83XX_FLASH_LOCK 0x8111c010 137 #define QLA83XX_FLASH_UNLOCK 0x8111c014 138 #define QLA83XX_DEV_PARTINFO1 0x221023e0 139 #define QLA83XX_DEV_PARTINFO2 0x221023e4 140 #define QLA83XX_FW_HEARTBEAT 0x221020b0 141 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8 142 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac 143 144 /* 83XX: Macros defining 8200 AEN Reason codes */ 145 #define IDC_DEVICE_STATE_CHANGE BIT_0 146 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1 147 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2 148 #define IDC_HEARTBEAT_FAILURE BIT_3 149 150 /* 83XX: Macros defining 8200 AEN Error-levels */ 151 #define ERR_LEVEL_NON_FATAL 0x1 152 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2 153 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4 154 155 /* 83XX: Macros for IDC Version */ 156 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01 157 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0 158 159 /* 83XX: Macros for scheduling dpc tasks */ 160 #define QLA83XX_NIC_CORE_RESET 0x1 161 #define QLA83XX_IDC_STATE_HANDLER 0x2 162 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3 163 164 /* 83XX: Macros for defining IDC-Control bits */ 165 #define QLA83XX_IDC_RESET_DISABLED BIT_0 166 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1 167 168 /* 83XX: Macros for different timeouts */ 169 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30 170 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10 171 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ) 172 173 /* 83XX: Macros for defining class in DEV-Partition Info register */ 174 #define QLA83XX_CLASS_TYPE_NONE 0x0 175 #define QLA83XX_CLASS_TYPE_NIC 0x1 176 #define QLA83XX_CLASS_TYPE_FCOE 0x2 177 #define QLA83XX_CLASS_TYPE_ISCSI 0x3 178 179 /* 83XX: Macros for IDC Lock-Recovery stages */ 180 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for 181 * lock-recovery 182 */ 183 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */ 184 185 /* 83XX: Macros for IDC Audit type */ 186 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of 187 * dev-state change to NEED-RESET 188 * or NEED-QUIESCENT 189 */ 190 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of 191 * reset-recovery completion is 192 * second 193 */ 194 /* ISP2031: Values for laser on/off */ 195 #define PORT_0_2031 0x00201340 196 #define PORT_1_2031 0x00201350 197 #define LASER_ON_2031 0x01800100 198 #define LASER_OFF_2031 0x01800180 199 200 /* 201 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an 202 * 133Mhz slot. 203 */ 204 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr)) 205 #define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr)) 206 207 /* 208 * Fibre Channel device definitions. 209 */ 210 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */ 211 #define MAX_FIBRE_DEVICES_2100 512 212 #define MAX_FIBRE_DEVICES_2400 2048 213 #define MAX_FIBRE_DEVICES_LOOP 128 214 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400 215 #define LOOPID_MAP_SIZE (ha->max_fibre_devices) 216 #define MAX_FIBRE_LUNS 0xFFFF 217 #define MAX_HOST_COUNT 16 218 219 /* 220 * Host adapter default definitions. 221 */ 222 #define MAX_BUSES 1 /* We only have one bus today */ 223 #define MIN_LUNS 8 224 #define MAX_LUNS MAX_FIBRE_LUNS 225 #define MAX_CMDS_PER_LUN 255 226 227 /* 228 * Fibre Channel device definitions. 229 */ 230 #define SNS_LAST_LOOP_ID_2100 0xfe 231 #define SNS_LAST_LOOP_ID_2300 0x7ff 232 233 #define LAST_LOCAL_LOOP_ID 0x7d 234 #define SNS_FL_PORT 0x7e 235 #define FABRIC_CONTROLLER 0x7f 236 #define SIMPLE_NAME_SERVER 0x80 237 #define SNS_FIRST_LOOP_ID 0x81 238 #define MANAGEMENT_SERVER 0xfe 239 #define BROADCAST 0xff 240 241 /* 242 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the 243 * valid range of an N-PORT id is 0 through 0x7ef. 244 */ 245 #define NPH_LAST_HANDLE 0x7ef 246 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */ 247 #define NPH_SNS 0x7fc /* FFFFFC */ 248 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */ 249 #define NPH_F_PORT 0x7fe /* FFFFFE */ 250 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */ 251 252 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */ 253 #include "qla_fw.h" 254 /* 255 * Timeout timer counts in seconds 256 */ 257 #define PORT_RETRY_TIME 1 258 #define LOOP_DOWN_TIMEOUT 60 259 #define LOOP_DOWN_TIME 255 /* 240 */ 260 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30) 261 262 #define DEFAULT_OUTSTANDING_COMMANDS 4096 263 #define MIN_OUTSTANDING_COMMANDS 128 264 265 /* ISP request and response entry counts (37-65535) */ 266 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */ 267 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */ 268 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */ 269 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */ 270 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/ 271 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/ 272 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/ 273 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/ 274 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */ 275 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/ 276 #define EXTENDED_EXCH_ENTRY_CNT 32768 /* Entries for offload case */ 277 278 struct req_que; 279 struct qla_tgt_sess; 280 281 /* 282 * SCSI Request Block 283 */ 284 struct srb_cmd { 285 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */ 286 uint32_t request_sense_length; 287 uint32_t fw_sense_length; 288 uint8_t *request_sense_ptr; 289 void *ctx; 290 }; 291 292 /* 293 * SRB flag definitions 294 */ 295 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 296 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */ 297 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */ 298 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */ 299 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */ 300 301 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */ 302 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID) 303 304 struct els_logo_payload { 305 uint8_t opcode; 306 uint8_t rsvd[3]; 307 uint8_t s_id[3]; 308 uint8_t rsvd1[1]; 309 uint8_t wwpn[WWN_SIZE]; 310 }; 311 312 /* 313 * SRB extensions. 314 */ 315 struct srb_iocb { 316 union { 317 struct { 318 uint16_t flags; 319 #define SRB_LOGIN_RETRIED BIT_0 320 #define SRB_LOGIN_COND_PLOGI BIT_1 321 #define SRB_LOGIN_SKIP_PRLI BIT_2 322 uint16_t data[2]; 323 } logio; 324 struct { 325 #define ELS_DCMD_TIMEOUT 20 326 #define ELS_DCMD_LOGO 0x5 327 uint32_t flags; 328 uint32_t els_cmd; 329 struct completion comp; 330 struct els_logo_payload *els_logo_pyld; 331 dma_addr_t els_logo_pyld_dma; 332 } els_logo; 333 struct { 334 /* 335 * Values for flags field below are as 336 * defined in tsk_mgmt_entry struct 337 * for control_flags field in qla_fw.h. 338 */ 339 uint64_t lun; 340 uint32_t flags; 341 uint32_t data; 342 struct completion comp; 343 __le16 comp_status; 344 } tmf; 345 struct { 346 #define SRB_FXDISC_REQ_DMA_VALID BIT_0 347 #define SRB_FXDISC_RESP_DMA_VALID BIT_1 348 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2 349 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3 350 #define FXDISC_TIMEOUT 20 351 uint8_t flags; 352 uint32_t req_len; 353 uint32_t rsp_len; 354 void *req_addr; 355 void *rsp_addr; 356 dma_addr_t req_dma_handle; 357 dma_addr_t rsp_dma_handle; 358 __le32 adapter_id; 359 __le32 adapter_id_hi; 360 __le16 req_func_type; 361 __le32 req_data; 362 __le32 req_data_extra; 363 __le32 result; 364 __le32 seq_number; 365 __le16 fw_flags; 366 struct completion fxiocb_comp; 367 __le32 reserved_0; 368 uint8_t reserved_1; 369 } fxiocb; 370 struct { 371 uint32_t cmd_hndl; 372 __le16 comp_status; 373 struct completion comp; 374 } abt; 375 } u; 376 377 struct timer_list timer; 378 void (*timeout)(void *); 379 }; 380 381 /* Values for srb_ctx type */ 382 #define SRB_LOGIN_CMD 1 383 #define SRB_LOGOUT_CMD 2 384 #define SRB_ELS_CMD_RPT 3 385 #define SRB_ELS_CMD_HST 4 386 #define SRB_CT_CMD 5 387 #define SRB_ADISC_CMD 6 388 #define SRB_TM_CMD 7 389 #define SRB_SCSI_CMD 8 390 #define SRB_BIDI_CMD 9 391 #define SRB_FXIOCB_DCMD 10 392 #define SRB_FXIOCB_BCMD 11 393 #define SRB_ABT_CMD 12 394 #define SRB_ELS_DCMD 13 395 396 typedef struct srb { 397 atomic_t ref_count; 398 struct fc_port *fcport; 399 uint32_t handle; 400 uint16_t flags; 401 uint16_t type; 402 char *name; 403 int iocbs; 404 union { 405 struct srb_iocb iocb_cmd; 406 struct fc_bsg_job *bsg_job; 407 struct srb_cmd scmd; 408 } u; 409 void (*done)(void *, void *, int); 410 void (*free)(void *, void *); 411 } srb_t; 412 413 #define GET_CMD_SP(sp) (sp->u.scmd.cmd) 414 #define SET_CMD_SP(sp, cmd) (sp->u.scmd.cmd = cmd) 415 #define GET_CMD_CTX_SP(sp) (sp->u.scmd.ctx) 416 417 #define GET_CMD_SENSE_LEN(sp) \ 418 (sp->u.scmd.request_sense_length) 419 #define SET_CMD_SENSE_LEN(sp, len) \ 420 (sp->u.scmd.request_sense_length = len) 421 #define GET_CMD_SENSE_PTR(sp) \ 422 (sp->u.scmd.request_sense_ptr) 423 #define SET_CMD_SENSE_PTR(sp, ptr) \ 424 (sp->u.scmd.request_sense_ptr = ptr) 425 #define GET_FW_SENSE_LEN(sp) \ 426 (sp->u.scmd.fw_sense_length) 427 #define SET_FW_SENSE_LEN(sp, len) \ 428 (sp->u.scmd.fw_sense_length = len) 429 430 struct msg_echo_lb { 431 dma_addr_t send_dma; 432 dma_addr_t rcv_dma; 433 uint16_t req_sg_cnt; 434 uint16_t rsp_sg_cnt; 435 uint16_t options; 436 uint32_t transfer_size; 437 uint32_t iteration_count; 438 }; 439 440 /* 441 * ISP I/O Register Set structure definitions. 442 */ 443 struct device_reg_2xxx { 444 uint16_t flash_address; /* Flash BIOS address */ 445 uint16_t flash_data; /* Flash BIOS data */ 446 uint16_t unused_1[1]; /* Gap */ 447 uint16_t ctrl_status; /* Control/Status */ 448 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */ 449 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */ 450 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 451 452 uint16_t ictrl; /* Interrupt control */ 453 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */ 454 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */ 455 456 uint16_t istatus; /* Interrupt status */ 457 #define ISR_RISC_INT BIT_3 /* RISC interrupt */ 458 459 uint16_t semaphore; /* Semaphore */ 460 uint16_t nvram; /* NVRAM register. */ 461 #define NVR_DESELECT 0 462 #define NVR_BUSY BIT_15 463 #define NVR_WRT_ENABLE BIT_14 /* Write enable */ 464 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */ 465 #define NVR_DATA_IN BIT_3 466 #define NVR_DATA_OUT BIT_2 467 #define NVR_SELECT BIT_1 468 #define NVR_CLOCK BIT_0 469 470 #define NVR_WAIT_CNT 20000 471 472 union { 473 struct { 474 uint16_t mailbox0; 475 uint16_t mailbox1; 476 uint16_t mailbox2; 477 uint16_t mailbox3; 478 uint16_t mailbox4; 479 uint16_t mailbox5; 480 uint16_t mailbox6; 481 uint16_t mailbox7; 482 uint16_t unused_2[59]; /* Gap */ 483 } __attribute__((packed)) isp2100; 484 struct { 485 /* Request Queue */ 486 uint16_t req_q_in; /* In-Pointer */ 487 uint16_t req_q_out; /* Out-Pointer */ 488 /* Response Queue */ 489 uint16_t rsp_q_in; /* In-Pointer */ 490 uint16_t rsp_q_out; /* Out-Pointer */ 491 492 /* RISC to Host Status */ 493 uint32_t host_status; 494 #define HSR_RISC_INT BIT_15 /* RISC interrupt */ 495 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */ 496 497 /* Host to Host Semaphore */ 498 uint16_t host_semaphore; 499 uint16_t unused_3[17]; /* Gap */ 500 uint16_t mailbox0; 501 uint16_t mailbox1; 502 uint16_t mailbox2; 503 uint16_t mailbox3; 504 uint16_t mailbox4; 505 uint16_t mailbox5; 506 uint16_t mailbox6; 507 uint16_t mailbox7; 508 uint16_t mailbox8; 509 uint16_t mailbox9; 510 uint16_t mailbox10; 511 uint16_t mailbox11; 512 uint16_t mailbox12; 513 uint16_t mailbox13; 514 uint16_t mailbox14; 515 uint16_t mailbox15; 516 uint16_t mailbox16; 517 uint16_t mailbox17; 518 uint16_t mailbox18; 519 uint16_t mailbox19; 520 uint16_t mailbox20; 521 uint16_t mailbox21; 522 uint16_t mailbox22; 523 uint16_t mailbox23; 524 uint16_t mailbox24; 525 uint16_t mailbox25; 526 uint16_t mailbox26; 527 uint16_t mailbox27; 528 uint16_t mailbox28; 529 uint16_t mailbox29; 530 uint16_t mailbox30; 531 uint16_t mailbox31; 532 uint16_t fb_cmd; 533 uint16_t unused_4[10]; /* Gap */ 534 } __attribute__((packed)) isp2300; 535 } u; 536 537 uint16_t fpm_diag_config; 538 uint16_t unused_5[0x4]; /* Gap */ 539 uint16_t risc_hw; 540 uint16_t unused_5_1; /* Gap */ 541 uint16_t pcr; /* Processor Control Register. */ 542 uint16_t unused_6[0x5]; /* Gap */ 543 uint16_t mctr; /* Memory Configuration and Timing. */ 544 uint16_t unused_7[0x3]; /* Gap */ 545 uint16_t fb_cmd_2100; /* Unused on 23XX */ 546 uint16_t unused_8[0x3]; /* Gap */ 547 uint16_t hccr; /* Host command & control register. */ 548 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */ 549 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */ 550 /* HCCR commands */ 551 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */ 552 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */ 553 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */ 554 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */ 555 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ 556 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ 557 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */ 558 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */ 559 560 uint16_t unused_9[5]; /* Gap */ 561 uint16_t gpiod; /* GPIO Data register. */ 562 uint16_t gpioe; /* GPIO Enable register. */ 563 #define GPIO_LED_MASK 0x00C0 564 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000 565 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040 566 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080 567 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0 568 #define GPIO_LED_ALL_OFF 0x0000 569 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */ 570 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */ 571 572 union { 573 struct { 574 uint16_t unused_10[8]; /* Gap */ 575 uint16_t mailbox8; 576 uint16_t mailbox9; 577 uint16_t mailbox10; 578 uint16_t mailbox11; 579 uint16_t mailbox12; 580 uint16_t mailbox13; 581 uint16_t mailbox14; 582 uint16_t mailbox15; 583 uint16_t mailbox16; 584 uint16_t mailbox17; 585 uint16_t mailbox18; 586 uint16_t mailbox19; 587 uint16_t mailbox20; 588 uint16_t mailbox21; 589 uint16_t mailbox22; 590 uint16_t mailbox23; /* Also probe reg. */ 591 } __attribute__((packed)) isp2200; 592 } u_end; 593 }; 594 595 struct device_reg_25xxmq { 596 uint32_t req_q_in; 597 uint32_t req_q_out; 598 uint32_t rsp_q_in; 599 uint32_t rsp_q_out; 600 uint32_t atio_q_in; 601 uint32_t atio_q_out; 602 }; 603 604 605 struct device_reg_fx00 { 606 uint32_t mailbox0; /* 00 */ 607 uint32_t mailbox1; /* 04 */ 608 uint32_t mailbox2; /* 08 */ 609 uint32_t mailbox3; /* 0C */ 610 uint32_t mailbox4; /* 10 */ 611 uint32_t mailbox5; /* 14 */ 612 uint32_t mailbox6; /* 18 */ 613 uint32_t mailbox7; /* 1C */ 614 uint32_t mailbox8; /* 20 */ 615 uint32_t mailbox9; /* 24 */ 616 uint32_t mailbox10; /* 28 */ 617 uint32_t mailbox11; 618 uint32_t mailbox12; 619 uint32_t mailbox13; 620 uint32_t mailbox14; 621 uint32_t mailbox15; 622 uint32_t mailbox16; 623 uint32_t mailbox17; 624 uint32_t mailbox18; 625 uint32_t mailbox19; 626 uint32_t mailbox20; 627 uint32_t mailbox21; 628 uint32_t mailbox22; 629 uint32_t mailbox23; 630 uint32_t mailbox24; 631 uint32_t mailbox25; 632 uint32_t mailbox26; 633 uint32_t mailbox27; 634 uint32_t mailbox28; 635 uint32_t mailbox29; 636 uint32_t mailbox30; 637 uint32_t mailbox31; 638 uint32_t aenmailbox0; 639 uint32_t aenmailbox1; 640 uint32_t aenmailbox2; 641 uint32_t aenmailbox3; 642 uint32_t aenmailbox4; 643 uint32_t aenmailbox5; 644 uint32_t aenmailbox6; 645 uint32_t aenmailbox7; 646 /* Request Queue. */ 647 uint32_t req_q_in; /* A0 - Request Queue In-Pointer */ 648 uint32_t req_q_out; /* A4 - Request Queue Out-Pointer */ 649 /* Response Queue. */ 650 uint32_t rsp_q_in; /* A8 - Response Queue In-Pointer */ 651 uint32_t rsp_q_out; /* AC - Response Queue Out-Pointer */ 652 /* Init values shadowed on FW Up Event */ 653 uint32_t initval0; /* B0 */ 654 uint32_t initval1; /* B4 */ 655 uint32_t initval2; /* B8 */ 656 uint32_t initval3; /* BC */ 657 uint32_t initval4; /* C0 */ 658 uint32_t initval5; /* C4 */ 659 uint32_t initval6; /* C8 */ 660 uint32_t initval7; /* CC */ 661 uint32_t fwheartbeat; /* D0 */ 662 uint32_t pseudoaen; /* D4 */ 663 }; 664 665 666 667 typedef union { 668 struct device_reg_2xxx isp; 669 struct device_reg_24xx isp24; 670 struct device_reg_25xxmq isp25mq; 671 struct device_reg_82xx isp82; 672 struct device_reg_fx00 ispfx00; 673 } __iomem device_reg_t; 674 675 #define ISP_REQ_Q_IN(ha, reg) \ 676 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 677 &(reg)->u.isp2100.mailbox4 : \ 678 &(reg)->u.isp2300.req_q_in) 679 #define ISP_REQ_Q_OUT(ha, reg) \ 680 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 681 &(reg)->u.isp2100.mailbox4 : \ 682 &(reg)->u.isp2300.req_q_out) 683 #define ISP_RSP_Q_IN(ha, reg) \ 684 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 685 &(reg)->u.isp2100.mailbox5 : \ 686 &(reg)->u.isp2300.rsp_q_in) 687 #define ISP_RSP_Q_OUT(ha, reg) \ 688 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 689 &(reg)->u.isp2100.mailbox5 : \ 690 &(reg)->u.isp2300.rsp_q_out) 691 692 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in) 693 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out) 694 695 #define MAILBOX_REG(ha, reg, num) \ 696 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 697 (num < 8 ? \ 698 &(reg)->u.isp2100.mailbox0 + (num) : \ 699 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \ 700 &(reg)->u.isp2300.mailbox0 + (num)) 701 #define RD_MAILBOX_REG(ha, reg, num) \ 702 RD_REG_WORD(MAILBOX_REG(ha, reg, num)) 703 #define WRT_MAILBOX_REG(ha, reg, num, data) \ 704 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data) 705 706 #define FB_CMD_REG(ha, reg) \ 707 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \ 708 &(reg)->fb_cmd_2100 : \ 709 &(reg)->u.isp2300.fb_cmd) 710 #define RD_FB_CMD_REG(ha, reg) \ 711 RD_REG_WORD(FB_CMD_REG(ha, reg)) 712 #define WRT_FB_CMD_REG(ha, reg, data) \ 713 WRT_REG_WORD(FB_CMD_REG(ha, reg), data) 714 715 typedef struct { 716 uint32_t out_mb; /* outbound from driver */ 717 uint32_t in_mb; /* Incoming from RISC */ 718 uint16_t mb[MAILBOX_REGISTER_COUNT]; 719 long buf_size; 720 void *bufp; 721 uint32_t tov; 722 uint8_t flags; 723 #define MBX_DMA_IN BIT_0 724 #define MBX_DMA_OUT BIT_1 725 #define IOCTL_CMD BIT_2 726 } mbx_cmd_t; 727 728 struct mbx_cmd_32 { 729 uint32_t out_mb; /* outbound from driver */ 730 uint32_t in_mb; /* Incoming from RISC */ 731 uint32_t mb[MAILBOX_REGISTER_COUNT]; 732 long buf_size; 733 void *bufp; 734 uint32_t tov; 735 uint8_t flags; 736 #define MBX_DMA_IN BIT_0 737 #define MBX_DMA_OUT BIT_1 738 #define IOCTL_CMD BIT_2 739 }; 740 741 742 #define MBX_TOV_SECONDS 30 743 744 /* 745 * ISP product identification definitions in mailboxes after reset. 746 */ 747 #define PROD_ID_1 0x4953 748 #define PROD_ID_2 0x0000 749 #define PROD_ID_2a 0x5020 750 #define PROD_ID_3 0x2020 751 752 /* 753 * ISP mailbox Self-Test status codes 754 */ 755 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 756 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 757 #define MBS_BUSY 4 /* Busy. */ 758 759 /* 760 * ISP mailbox command complete status codes 761 */ 762 #define MBS_COMMAND_COMPLETE 0x4000 763 #define MBS_INVALID_COMMAND 0x4001 764 #define MBS_HOST_INTERFACE_ERROR 0x4002 765 #define MBS_TEST_FAILED 0x4003 766 #define MBS_COMMAND_ERROR 0x4005 767 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 768 #define MBS_PORT_ID_USED 0x4007 769 #define MBS_LOOP_ID_USED 0x4008 770 #define MBS_ALL_IDS_IN_USE 0x4009 771 #define MBS_NOT_LOGGED_IN 0x400A 772 #define MBS_LINK_DOWN_ERROR 0x400B 773 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C 774 775 /* 776 * ISP mailbox asynchronous event status codes 777 */ 778 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 779 #define MBA_RESET 0x8001 /* Reset Detected. */ 780 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 781 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 782 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 783 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 784 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 785 /* occurred. */ 786 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 787 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 788 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 789 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 790 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */ 791 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 792 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */ 793 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */ 794 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 795 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 796 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 797 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 798 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 799 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 800 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 801 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 802 /* used. */ 803 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */ 804 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 805 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 806 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 807 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 808 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 809 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 810 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 811 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */ 812 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */ 813 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 814 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */ 815 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */ 816 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */ 817 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */ 818 #define MBA_FW_STARTING 0x8051 /* Firmware starting */ 819 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */ 820 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */ 821 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */ 822 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */ 823 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */ 824 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */ 825 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change 826 Notification */ 827 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */ 828 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */ 829 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */ 830 /* 83XX FCoE specific */ 831 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */ 832 833 /* Interrupt type codes */ 834 #define INTR_ROM_MB_SUCCESS 0x1 835 #define INTR_ROM_MB_FAILED 0x2 836 #define INTR_MB_SUCCESS 0x10 837 #define INTR_MB_FAILED 0x11 838 #define INTR_ASYNC_EVENT 0x12 839 #define INTR_RSP_QUE_UPDATE 0x13 840 #define INTR_RSP_QUE_UPDATE_83XX 0x14 841 #define INTR_ATIO_QUE_UPDATE 0x1C 842 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D 843 844 /* ISP mailbox loopback echo diagnostic error code */ 845 #define MBS_LB_RESET 0x17 846 /* 847 * Firmware options 1, 2, 3. 848 */ 849 #define FO1_AE_ON_LIPF8 BIT_0 850 #define FO1_AE_ALL_LIP_RESET BIT_1 851 #define FO1_CTIO_RETRY BIT_3 852 #define FO1_DISABLE_LIP_F7_SW BIT_4 853 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 854 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */ 855 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7 856 #define FO1_SET_EMPHASIS_SWING BIT_8 857 #define FO1_AE_AUTO_BYPASS BIT_9 858 #define FO1_ENABLE_PURE_IOCB BIT_10 859 #define FO1_AE_PLOGI_RJT BIT_11 860 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 861 #define FO1_AE_QUEUE_FULL BIT_13 862 863 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 864 #define FO2_REV_LOOPBACK BIT_1 865 866 #define FO3_ENABLE_EMERG_IOCB BIT_0 867 #define FO3_AE_RND_ERROR BIT_1 868 869 /* 24XX additional firmware options */ 870 #define ADD_FO_COUNT 3 871 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */ 872 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10 873 874 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5 875 876 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14 877 878 /* 879 * ISP mailbox commands 880 */ 881 #define MBC_LOAD_RAM 1 /* Load RAM. */ 882 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 883 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 884 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 885 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 886 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */ 887 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */ 888 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */ 889 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */ 890 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */ 891 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */ 892 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 893 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */ 894 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */ 895 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */ 896 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 897 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 898 #define MBC_RESET 0x18 /* Reset. */ 899 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */ 900 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */ 901 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */ 902 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */ 903 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */ 904 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/ 905 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */ 906 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 907 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 908 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 909 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 910 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */ 911 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 912 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 913 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */ 914 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */ 915 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 916 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */ 917 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */ 918 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 919 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */ 920 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */ 921 #define MBC_DATA_RATE 0x5d /* Data Rate */ 922 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 923 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */ 924 /* Initialization Procedure */ 925 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 926 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 927 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 928 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 929 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 930 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 931 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 932 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 933 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */ 934 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 935 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 936 /* commandd. */ 937 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 938 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 939 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 940 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 941 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 942 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */ 943 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */ 944 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */ 945 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */ 946 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */ 947 #define MBC_LUN_RESET 0x7E /* Send LUN reset */ 948 949 /* 950 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones 951 * should be defined with MBC_MR_* 952 */ 953 #define MBC_MR_DRV_SHUTDOWN 0x6A 954 955 /* 956 * ISP24xx mailbox commands 957 */ 958 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */ 959 #define MBC_READ_SERDES 0x4 /* Read serdes word. */ 960 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */ 961 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */ 962 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */ 963 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */ 964 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */ 965 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */ 966 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */ 967 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */ 968 #define MBC_READ_SFP 0x31 /* Read SFP Data. */ 969 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */ 970 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */ 971 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */ 972 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */ 973 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */ 974 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */ 975 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */ 976 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */ 977 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */ 978 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */ 979 #define MBC_PORT_RESET 0x120 /* Port Reset */ 980 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 981 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 982 983 /* 984 * ISP81xx mailbox commands 985 */ 986 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */ 987 988 /* 989 * ISP8044 mailbox commands 990 */ 991 #define MBC_SET_GET_ETH_SERDES_REG 0x150 992 #define HCS_WRITE_SERDES 0x3 993 #define HCS_READ_SERDES 0x4 994 995 /* Firmware return data sizes */ 996 #define FCAL_MAP_SIZE 128 997 998 /* Mailbox bit definitions for out_mb and in_mb */ 999 #define MBX_31 BIT_31 1000 #define MBX_30 BIT_30 1001 #define MBX_29 BIT_29 1002 #define MBX_28 BIT_28 1003 #define MBX_27 BIT_27 1004 #define MBX_26 BIT_26 1005 #define MBX_25 BIT_25 1006 #define MBX_24 BIT_24 1007 #define MBX_23 BIT_23 1008 #define MBX_22 BIT_22 1009 #define MBX_21 BIT_21 1010 #define MBX_20 BIT_20 1011 #define MBX_19 BIT_19 1012 #define MBX_18 BIT_18 1013 #define MBX_17 BIT_17 1014 #define MBX_16 BIT_16 1015 #define MBX_15 BIT_15 1016 #define MBX_14 BIT_14 1017 #define MBX_13 BIT_13 1018 #define MBX_12 BIT_12 1019 #define MBX_11 BIT_11 1020 #define MBX_10 BIT_10 1021 #define MBX_9 BIT_9 1022 #define MBX_8 BIT_8 1023 #define MBX_7 BIT_7 1024 #define MBX_6 BIT_6 1025 #define MBX_5 BIT_5 1026 #define MBX_4 BIT_4 1027 #define MBX_3 BIT_3 1028 #define MBX_2 BIT_2 1029 #define MBX_1 BIT_1 1030 #define MBX_0 BIT_0 1031 1032 #define RNID_TYPE_SET_VERSION 0x9 1033 #define RNID_TYPE_ASIC_TEMP 0xC 1034 1035 /* 1036 * Firmware state codes from get firmware state mailbox command 1037 */ 1038 #define FSTATE_CONFIG_WAIT 0 1039 #define FSTATE_WAIT_AL_PA 1 1040 #define FSTATE_WAIT_LOGIN 2 1041 #define FSTATE_READY 3 1042 #define FSTATE_LOSS_OF_SYNC 4 1043 #define FSTATE_ERROR 5 1044 #define FSTATE_REINIT 6 1045 #define FSTATE_NON_PART 7 1046 1047 #define FSTATE_CONFIG_CORRECT 0 1048 #define FSTATE_P2P_RCV_LIP 1 1049 #define FSTATE_P2P_CHOOSE_LOOP 2 1050 #define FSTATE_P2P_RCV_UNIDEN_LIP 3 1051 #define FSTATE_FATAL_ERROR 4 1052 #define FSTATE_LOOP_BACK_CONN 5 1053 1054 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01 1055 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00 1056 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE 1057 #define QLA27XX_PRIMARY_IMAGE 1 1058 #define QLA27XX_SECONDARY_IMAGE 2 1059 1060 /* 1061 * Port Database structure definition 1062 * Little endian except where noted. 1063 */ 1064 #define PORT_DATABASE_SIZE 128 /* bytes */ 1065 typedef struct { 1066 uint8_t options; 1067 uint8_t control; 1068 uint8_t master_state; 1069 uint8_t slave_state; 1070 uint8_t reserved[2]; 1071 uint8_t hard_address; 1072 uint8_t reserved_1; 1073 uint8_t port_id[4]; 1074 uint8_t node_name[WWN_SIZE]; 1075 uint8_t port_name[WWN_SIZE]; 1076 uint16_t execution_throttle; 1077 uint16_t execution_count; 1078 uint8_t reset_count; 1079 uint8_t reserved_2; 1080 uint16_t resource_allocation; 1081 uint16_t current_allocation; 1082 uint16_t queue_head; 1083 uint16_t queue_tail; 1084 uint16_t transmit_execution_list_next; 1085 uint16_t transmit_execution_list_previous; 1086 uint16_t common_features; 1087 uint16_t total_concurrent_sequences; 1088 uint16_t RO_by_information_category; 1089 uint8_t recipient; 1090 uint8_t initiator; 1091 uint16_t receive_data_size; 1092 uint16_t concurrent_sequences; 1093 uint16_t open_sequences_per_exchange; 1094 uint16_t lun_abort_flags; 1095 uint16_t lun_stop_flags; 1096 uint16_t stop_queue_head; 1097 uint16_t stop_queue_tail; 1098 uint16_t port_retry_timer; 1099 uint16_t next_sequence_id; 1100 uint16_t frame_count; 1101 uint16_t PRLI_payload_length; 1102 uint8_t prli_svc_param_word_0[2]; /* Big endian */ 1103 /* Bits 15-0 of word 0 */ 1104 uint8_t prli_svc_param_word_3[2]; /* Big endian */ 1105 /* Bits 15-0 of word 3 */ 1106 uint16_t loop_id; 1107 uint16_t extended_lun_info_list_pointer; 1108 uint16_t extended_lun_stop_list_pointer; 1109 } port_database_t; 1110 1111 /* 1112 * Port database slave/master states 1113 */ 1114 #define PD_STATE_DISCOVERY 0 1115 #define PD_STATE_WAIT_DISCOVERY_ACK 1 1116 #define PD_STATE_PORT_LOGIN 2 1117 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 1118 #define PD_STATE_PROCESS_LOGIN 4 1119 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 1120 #define PD_STATE_PORT_LOGGED_IN 6 1121 #define PD_STATE_PORT_UNAVAILABLE 7 1122 #define PD_STATE_PROCESS_LOGOUT 8 1123 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 1124 #define PD_STATE_PORT_LOGOUT 10 1125 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 1126 1127 1128 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1) 1129 #define QLA_ZIO_DISABLED 0 1130 #define QLA_ZIO_DEFAULT_TIMER 2 1131 1132 /* 1133 * ISP Initialization Control Block. 1134 * Little endian except where noted. 1135 */ 1136 #define ICB_VERSION 1 1137 typedef struct { 1138 uint8_t version; 1139 uint8_t reserved_1; 1140 1141 /* 1142 * LSB BIT 0 = Enable Hard Loop Id 1143 * LSB BIT 1 = Enable Fairness 1144 * LSB BIT 2 = Enable Full-Duplex 1145 * LSB BIT 3 = Enable Fast Posting 1146 * LSB BIT 4 = Enable Target Mode 1147 * LSB BIT 5 = Disable Initiator Mode 1148 * LSB BIT 6 = Enable ADISC 1149 * LSB BIT 7 = Enable Target Inquiry Data 1150 * 1151 * MSB BIT 0 = Enable PDBC Notify 1152 * MSB BIT 1 = Non Participating LIP 1153 * MSB BIT 2 = Descending Loop ID Search 1154 * MSB BIT 3 = Acquire Loop ID in LIPA 1155 * MSB BIT 4 = Stop PortQ on Full Status 1156 * MSB BIT 5 = Full Login after LIP 1157 * MSB BIT 6 = Node Name Option 1158 * MSB BIT 7 = Ext IFWCB enable bit 1159 */ 1160 uint8_t firmware_options[2]; 1161 1162 uint16_t frame_payload_size; 1163 uint16_t max_iocb_allocation; 1164 uint16_t execution_throttle; 1165 uint8_t retry_count; 1166 uint8_t retry_delay; /* unused */ 1167 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1168 uint16_t hard_address; 1169 uint8_t inquiry_data; 1170 uint8_t login_timeout; 1171 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1172 1173 uint16_t request_q_outpointer; 1174 uint16_t response_q_inpointer; 1175 uint16_t request_q_length; 1176 uint16_t response_q_length; 1177 uint32_t request_q_address[2]; 1178 uint32_t response_q_address[2]; 1179 1180 uint16_t lun_enables; 1181 uint8_t command_resource_count; 1182 uint8_t immediate_notify_resource_count; 1183 uint16_t timeout; 1184 uint8_t reserved_2[2]; 1185 1186 /* 1187 * LSB BIT 0 = Timer Operation mode bit 0 1188 * LSB BIT 1 = Timer Operation mode bit 1 1189 * LSB BIT 2 = Timer Operation mode bit 2 1190 * LSB BIT 3 = Timer Operation mode bit 3 1191 * LSB BIT 4 = Init Config Mode bit 0 1192 * LSB BIT 5 = Init Config Mode bit 1 1193 * LSB BIT 6 = Init Config Mode bit 2 1194 * LSB BIT 7 = Enable Non part on LIHA failure 1195 * 1196 * MSB BIT 0 = Enable class 2 1197 * MSB BIT 1 = Enable ACK0 1198 * MSB BIT 2 = 1199 * MSB BIT 3 = 1200 * MSB BIT 4 = FC Tape Enable 1201 * MSB BIT 5 = Enable FC Confirm 1202 * MSB BIT 6 = Enable command queuing in target mode 1203 * MSB BIT 7 = No Logo On Link Down 1204 */ 1205 uint8_t add_firmware_options[2]; 1206 1207 uint8_t response_accumulation_timer; 1208 uint8_t interrupt_delay_timer; 1209 1210 /* 1211 * LSB BIT 0 = Enable Read xfr_rdy 1212 * LSB BIT 1 = Soft ID only 1213 * LSB BIT 2 = 1214 * LSB BIT 3 = 1215 * LSB BIT 4 = FCP RSP Payload [0] 1216 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1217 * LSB BIT 6 = Enable Out-of-Order frame handling 1218 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1219 * 1220 * MSB BIT 0 = Sbus enable - 2300 1221 * MSB BIT 1 = 1222 * MSB BIT 2 = 1223 * MSB BIT 3 = 1224 * MSB BIT 4 = LED mode 1225 * MSB BIT 5 = enable 50 ohm termination 1226 * MSB BIT 6 = Data Rate (2300 only) 1227 * MSB BIT 7 = Data Rate (2300 only) 1228 */ 1229 uint8_t special_options[2]; 1230 1231 uint8_t reserved_3[26]; 1232 } init_cb_t; 1233 1234 /* 1235 * Get Link Status mailbox command return buffer. 1236 */ 1237 #define GLSO_SEND_RPS BIT_0 1238 #define GLSO_USE_DID BIT_3 1239 1240 struct link_statistics { 1241 uint32_t link_fail_cnt; 1242 uint32_t loss_sync_cnt; 1243 uint32_t loss_sig_cnt; 1244 uint32_t prim_seq_err_cnt; 1245 uint32_t inval_xmit_word_cnt; 1246 uint32_t inval_crc_cnt; 1247 uint32_t lip_cnt; 1248 uint32_t link_up_cnt; 1249 uint32_t link_down_loop_init_tmo; 1250 uint32_t link_down_los; 1251 uint32_t link_down_loss_rcv_clk; 1252 uint32_t reserved0[5]; 1253 uint32_t port_cfg_chg; 1254 uint32_t reserved1[11]; 1255 uint32_t rsp_q_full; 1256 uint32_t atio_q_full; 1257 uint32_t drop_ae; 1258 uint32_t els_proto_err; 1259 uint32_t reserved2; 1260 uint32_t tx_frames; 1261 uint32_t rx_frames; 1262 uint32_t discarded_frames; 1263 uint32_t dropped_frames; 1264 uint32_t reserved3; 1265 uint32_t nos_rcvd; 1266 uint32_t reserved4[4]; 1267 uint32_t tx_prjt; 1268 uint32_t rcv_exfail; 1269 uint32_t rcv_abts; 1270 uint32_t seq_frm_miss; 1271 uint32_t corr_err; 1272 uint32_t mb_rqst; 1273 uint32_t nport_full; 1274 uint32_t eofa; 1275 uint32_t reserved5; 1276 uint32_t fpm_recv_word_cnt_lo; 1277 uint32_t fpm_recv_word_cnt_hi; 1278 uint32_t fpm_disc_word_cnt_lo; 1279 uint32_t fpm_disc_word_cnt_hi; 1280 uint32_t fpm_xmit_word_cnt_lo; 1281 uint32_t fpm_xmit_word_cnt_hi; 1282 uint32_t reserved6[70]; 1283 }; 1284 1285 /* 1286 * NVRAM Command values. 1287 */ 1288 #define NV_START_BIT BIT_2 1289 #define NV_WRITE_OP (BIT_26+BIT_24) 1290 #define NV_READ_OP (BIT_26+BIT_25) 1291 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24) 1292 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24) 1293 #define NV_DELAY_COUNT 10 1294 1295 /* 1296 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition. 1297 */ 1298 typedef struct { 1299 /* 1300 * NVRAM header 1301 */ 1302 uint8_t id[4]; 1303 uint8_t nvram_version; 1304 uint8_t reserved_0; 1305 1306 /* 1307 * NVRAM RISC parameter block 1308 */ 1309 uint8_t parameter_block_version; 1310 uint8_t reserved_1; 1311 1312 /* 1313 * LSB BIT 0 = Enable Hard Loop Id 1314 * LSB BIT 1 = Enable Fairness 1315 * LSB BIT 2 = Enable Full-Duplex 1316 * LSB BIT 3 = Enable Fast Posting 1317 * LSB BIT 4 = Enable Target Mode 1318 * LSB BIT 5 = Disable Initiator Mode 1319 * LSB BIT 6 = Enable ADISC 1320 * LSB BIT 7 = Enable Target Inquiry Data 1321 * 1322 * MSB BIT 0 = Enable PDBC Notify 1323 * MSB BIT 1 = Non Participating LIP 1324 * MSB BIT 2 = Descending Loop ID Search 1325 * MSB BIT 3 = Acquire Loop ID in LIPA 1326 * MSB BIT 4 = Stop PortQ on Full Status 1327 * MSB BIT 5 = Full Login after LIP 1328 * MSB BIT 6 = Node Name Option 1329 * MSB BIT 7 = Ext IFWCB enable bit 1330 */ 1331 uint8_t firmware_options[2]; 1332 1333 uint16_t frame_payload_size; 1334 uint16_t max_iocb_allocation; 1335 uint16_t execution_throttle; 1336 uint8_t retry_count; 1337 uint8_t retry_delay; /* unused */ 1338 uint8_t port_name[WWN_SIZE]; /* Big endian. */ 1339 uint16_t hard_address; 1340 uint8_t inquiry_data; 1341 uint8_t login_timeout; 1342 uint8_t node_name[WWN_SIZE]; /* Big endian. */ 1343 1344 /* 1345 * LSB BIT 0 = Timer Operation mode bit 0 1346 * LSB BIT 1 = Timer Operation mode bit 1 1347 * LSB BIT 2 = Timer Operation mode bit 2 1348 * LSB BIT 3 = Timer Operation mode bit 3 1349 * LSB BIT 4 = Init Config Mode bit 0 1350 * LSB BIT 5 = Init Config Mode bit 1 1351 * LSB BIT 6 = Init Config Mode bit 2 1352 * LSB BIT 7 = Enable Non part on LIHA failure 1353 * 1354 * MSB BIT 0 = Enable class 2 1355 * MSB BIT 1 = Enable ACK0 1356 * MSB BIT 2 = 1357 * MSB BIT 3 = 1358 * MSB BIT 4 = FC Tape Enable 1359 * MSB BIT 5 = Enable FC Confirm 1360 * MSB BIT 6 = Enable command queuing in target mode 1361 * MSB BIT 7 = No Logo On Link Down 1362 */ 1363 uint8_t add_firmware_options[2]; 1364 1365 uint8_t response_accumulation_timer; 1366 uint8_t interrupt_delay_timer; 1367 1368 /* 1369 * LSB BIT 0 = Enable Read xfr_rdy 1370 * LSB BIT 1 = Soft ID only 1371 * LSB BIT 2 = 1372 * LSB BIT 3 = 1373 * LSB BIT 4 = FCP RSP Payload [0] 1374 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200 1375 * LSB BIT 6 = Enable Out-of-Order frame handling 1376 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop 1377 * 1378 * MSB BIT 0 = Sbus enable - 2300 1379 * MSB BIT 1 = 1380 * MSB BIT 2 = 1381 * MSB BIT 3 = 1382 * MSB BIT 4 = LED mode 1383 * MSB BIT 5 = enable 50 ohm termination 1384 * MSB BIT 6 = Data Rate (2300 only) 1385 * MSB BIT 7 = Data Rate (2300 only) 1386 */ 1387 uint8_t special_options[2]; 1388 1389 /* Reserved for expanded RISC parameter block */ 1390 uint8_t reserved_2[22]; 1391 1392 /* 1393 * LSB BIT 0 = Tx Sensitivity 1G bit 0 1394 * LSB BIT 1 = Tx Sensitivity 1G bit 1 1395 * LSB BIT 2 = Tx Sensitivity 1G bit 2 1396 * LSB BIT 3 = Tx Sensitivity 1G bit 3 1397 * LSB BIT 4 = Rx Sensitivity 1G bit 0 1398 * LSB BIT 5 = Rx Sensitivity 1G bit 1 1399 * LSB BIT 6 = Rx Sensitivity 1G bit 2 1400 * LSB BIT 7 = Rx Sensitivity 1G bit 3 1401 * 1402 * MSB BIT 0 = Tx Sensitivity 2G bit 0 1403 * MSB BIT 1 = Tx Sensitivity 2G bit 1 1404 * MSB BIT 2 = Tx Sensitivity 2G bit 2 1405 * MSB BIT 3 = Tx Sensitivity 2G bit 3 1406 * MSB BIT 4 = Rx Sensitivity 2G bit 0 1407 * MSB BIT 5 = Rx Sensitivity 2G bit 1 1408 * MSB BIT 6 = Rx Sensitivity 2G bit 2 1409 * MSB BIT 7 = Rx Sensitivity 2G bit 3 1410 * 1411 * LSB BIT 0 = Output Swing 1G bit 0 1412 * LSB BIT 1 = Output Swing 1G bit 1 1413 * LSB BIT 2 = Output Swing 1G bit 2 1414 * LSB BIT 3 = Output Emphasis 1G bit 0 1415 * LSB BIT 4 = Output Emphasis 1G bit 1 1416 * LSB BIT 5 = Output Swing 2G bit 0 1417 * LSB BIT 6 = Output Swing 2G bit 1 1418 * LSB BIT 7 = Output Swing 2G bit 2 1419 * 1420 * MSB BIT 0 = Output Emphasis 2G bit 0 1421 * MSB BIT 1 = Output Emphasis 2G bit 1 1422 * MSB BIT 2 = Output Enable 1423 * MSB BIT 3 = 1424 * MSB BIT 4 = 1425 * MSB BIT 5 = 1426 * MSB BIT 6 = 1427 * MSB BIT 7 = 1428 */ 1429 uint8_t seriallink_options[4]; 1430 1431 /* 1432 * NVRAM host parameter block 1433 * 1434 * LSB BIT 0 = Enable spinup delay 1435 * LSB BIT 1 = Disable BIOS 1436 * LSB BIT 2 = Enable Memory Map BIOS 1437 * LSB BIT 3 = Enable Selectable Boot 1438 * LSB BIT 4 = Disable RISC code load 1439 * LSB BIT 5 = Set cache line size 1 1440 * LSB BIT 6 = PCI Parity Disable 1441 * LSB BIT 7 = Enable extended logging 1442 * 1443 * MSB BIT 0 = Enable 64bit addressing 1444 * MSB BIT 1 = Enable lip reset 1445 * MSB BIT 2 = Enable lip full login 1446 * MSB BIT 3 = Enable target reset 1447 * MSB BIT 4 = Enable database storage 1448 * MSB BIT 5 = Enable cache flush read 1449 * MSB BIT 6 = Enable database load 1450 * MSB BIT 7 = Enable alternate WWN 1451 */ 1452 uint8_t host_p[2]; 1453 1454 uint8_t boot_node_name[WWN_SIZE]; 1455 uint8_t boot_lun_number; 1456 uint8_t reset_delay; 1457 uint8_t port_down_retry_count; 1458 uint8_t boot_id_number; 1459 uint16_t max_luns_per_target; 1460 uint8_t fcode_boot_port_name[WWN_SIZE]; 1461 uint8_t alternate_port_name[WWN_SIZE]; 1462 uint8_t alternate_node_name[WWN_SIZE]; 1463 1464 /* 1465 * BIT 0 = Selective Login 1466 * BIT 1 = Alt-Boot Enable 1467 * BIT 2 = 1468 * BIT 3 = Boot Order List 1469 * BIT 4 = 1470 * BIT 5 = Selective LUN 1471 * BIT 6 = 1472 * BIT 7 = unused 1473 */ 1474 uint8_t efi_parameters; 1475 1476 uint8_t link_down_timeout; 1477 1478 uint8_t adapter_id[16]; 1479 1480 uint8_t alt1_boot_node_name[WWN_SIZE]; 1481 uint16_t alt1_boot_lun_number; 1482 uint8_t alt2_boot_node_name[WWN_SIZE]; 1483 uint16_t alt2_boot_lun_number; 1484 uint8_t alt3_boot_node_name[WWN_SIZE]; 1485 uint16_t alt3_boot_lun_number; 1486 uint8_t alt4_boot_node_name[WWN_SIZE]; 1487 uint16_t alt4_boot_lun_number; 1488 uint8_t alt5_boot_node_name[WWN_SIZE]; 1489 uint16_t alt5_boot_lun_number; 1490 uint8_t alt6_boot_node_name[WWN_SIZE]; 1491 uint16_t alt6_boot_lun_number; 1492 uint8_t alt7_boot_node_name[WWN_SIZE]; 1493 uint16_t alt7_boot_lun_number; 1494 1495 uint8_t reserved_3[2]; 1496 1497 /* Offset 200-215 : Model Number */ 1498 uint8_t model_number[16]; 1499 1500 /* OEM related items */ 1501 uint8_t oem_specific[16]; 1502 1503 /* 1504 * NVRAM Adapter Features offset 232-239 1505 * 1506 * LSB BIT 0 = External GBIC 1507 * LSB BIT 1 = Risc RAM parity 1508 * LSB BIT 2 = Buffer Plus Module 1509 * LSB BIT 3 = Multi Chip Adapter 1510 * LSB BIT 4 = Internal connector 1511 * LSB BIT 5 = 1512 * LSB BIT 6 = 1513 * LSB BIT 7 = 1514 * 1515 * MSB BIT 0 = 1516 * MSB BIT 1 = 1517 * MSB BIT 2 = 1518 * MSB BIT 3 = 1519 * MSB BIT 4 = 1520 * MSB BIT 5 = 1521 * MSB BIT 6 = 1522 * MSB BIT 7 = 1523 */ 1524 uint8_t adapter_features[2]; 1525 1526 uint8_t reserved_4[16]; 1527 1528 /* Subsystem vendor ID for ISP2200 */ 1529 uint16_t subsystem_vendor_id_2200; 1530 1531 /* Subsystem device ID for ISP2200 */ 1532 uint16_t subsystem_device_id_2200; 1533 1534 uint8_t reserved_5; 1535 uint8_t checksum; 1536 } nvram_t; 1537 1538 /* 1539 * ISP queue - response queue entry definition. 1540 */ 1541 typedef struct { 1542 uint8_t entry_type; /* Entry type. */ 1543 uint8_t entry_count; /* Entry count. */ 1544 uint8_t sys_define; /* System defined. */ 1545 uint8_t entry_status; /* Entry Status. */ 1546 uint32_t handle; /* System defined handle */ 1547 uint8_t data[52]; 1548 uint32_t signature; 1549 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */ 1550 } response_t; 1551 1552 /* 1553 * ISP queue - ATIO queue entry definition. 1554 */ 1555 struct atio { 1556 uint8_t entry_type; /* Entry type. */ 1557 uint8_t entry_count; /* Entry count. */ 1558 __le16 attr_n_length; 1559 uint8_t data[56]; 1560 uint32_t signature; 1561 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */ 1562 }; 1563 1564 typedef union { 1565 uint16_t extended; 1566 struct { 1567 uint8_t reserved; 1568 uint8_t standard; 1569 } id; 1570 } target_id_t; 1571 1572 #define SET_TARGET_ID(ha, to, from) \ 1573 do { \ 1574 if (HAS_EXTENDED_IDS(ha)) \ 1575 to.extended = cpu_to_le16(from); \ 1576 else \ 1577 to.id.standard = (uint8_t)from; \ 1578 } while (0) 1579 1580 /* 1581 * ISP queue - command entry structure definition. 1582 */ 1583 #define COMMAND_TYPE 0x11 /* Command entry */ 1584 typedef struct { 1585 uint8_t entry_type; /* Entry type. */ 1586 uint8_t entry_count; /* Entry count. */ 1587 uint8_t sys_define; /* System defined. */ 1588 uint8_t entry_status; /* Entry Status. */ 1589 uint32_t handle; /* System handle. */ 1590 target_id_t target; /* SCSI ID */ 1591 uint16_t lun; /* SCSI LUN */ 1592 uint16_t control_flags; /* Control flags. */ 1593 #define CF_WRITE BIT_6 1594 #define CF_READ BIT_5 1595 #define CF_SIMPLE_TAG BIT_3 1596 #define CF_ORDERED_TAG BIT_2 1597 #define CF_HEAD_TAG BIT_1 1598 uint16_t reserved_1; 1599 uint16_t timeout; /* Command timeout. */ 1600 uint16_t dseg_count; /* Data segment count. */ 1601 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1602 uint32_t byte_count; /* Total byte count. */ 1603 uint32_t dseg_0_address; /* Data segment 0 address. */ 1604 uint32_t dseg_0_length; /* Data segment 0 length. */ 1605 uint32_t dseg_1_address; /* Data segment 1 address. */ 1606 uint32_t dseg_1_length; /* Data segment 1 length. */ 1607 uint32_t dseg_2_address; /* Data segment 2 address. */ 1608 uint32_t dseg_2_length; /* Data segment 2 length. */ 1609 } cmd_entry_t; 1610 1611 /* 1612 * ISP queue - 64-Bit addressing, command entry structure definition. 1613 */ 1614 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */ 1615 typedef struct { 1616 uint8_t entry_type; /* Entry type. */ 1617 uint8_t entry_count; /* Entry count. */ 1618 uint8_t sys_define; /* System defined. */ 1619 uint8_t entry_status; /* Entry Status. */ 1620 uint32_t handle; /* System handle. */ 1621 target_id_t target; /* SCSI ID */ 1622 uint16_t lun; /* SCSI LUN */ 1623 uint16_t control_flags; /* Control flags. */ 1624 uint16_t reserved_1; 1625 uint16_t timeout; /* Command timeout. */ 1626 uint16_t dseg_count; /* Data segment count. */ 1627 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ 1628 uint32_t byte_count; /* Total byte count. */ 1629 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1630 uint32_t dseg_0_length; /* Data segment 0 length. */ 1631 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1632 uint32_t dseg_1_length; /* Data segment 1 length. */ 1633 } cmd_a64_entry_t, request_t; 1634 1635 /* 1636 * ISP queue - continuation entry structure definition. 1637 */ 1638 #define CONTINUE_TYPE 0x02 /* Continuation entry. */ 1639 typedef struct { 1640 uint8_t entry_type; /* Entry type. */ 1641 uint8_t entry_count; /* Entry count. */ 1642 uint8_t sys_define; /* System defined. */ 1643 uint8_t entry_status; /* Entry Status. */ 1644 uint32_t reserved; 1645 uint32_t dseg_0_address; /* Data segment 0 address. */ 1646 uint32_t dseg_0_length; /* Data segment 0 length. */ 1647 uint32_t dseg_1_address; /* Data segment 1 address. */ 1648 uint32_t dseg_1_length; /* Data segment 1 length. */ 1649 uint32_t dseg_2_address; /* Data segment 2 address. */ 1650 uint32_t dseg_2_length; /* Data segment 2 length. */ 1651 uint32_t dseg_3_address; /* Data segment 3 address. */ 1652 uint32_t dseg_3_length; /* Data segment 3 length. */ 1653 uint32_t dseg_4_address; /* Data segment 4 address. */ 1654 uint32_t dseg_4_length; /* Data segment 4 length. */ 1655 uint32_t dseg_5_address; /* Data segment 5 address. */ 1656 uint32_t dseg_5_length; /* Data segment 5 length. */ 1657 uint32_t dseg_6_address; /* Data segment 6 address. */ 1658 uint32_t dseg_6_length; /* Data segment 6 length. */ 1659 } cont_entry_t; 1660 1661 /* 1662 * ISP queue - 64-Bit addressing, continuation entry structure definition. 1663 */ 1664 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */ 1665 typedef struct { 1666 uint8_t entry_type; /* Entry type. */ 1667 uint8_t entry_count; /* Entry count. */ 1668 uint8_t sys_define; /* System defined. */ 1669 uint8_t entry_status; /* Entry Status. */ 1670 uint32_t dseg_0_address[2]; /* Data segment 0 address. */ 1671 uint32_t dseg_0_length; /* Data segment 0 length. */ 1672 uint32_t dseg_1_address[2]; /* Data segment 1 address. */ 1673 uint32_t dseg_1_length; /* Data segment 1 length. */ 1674 uint32_t dseg_2_address [2]; /* Data segment 2 address. */ 1675 uint32_t dseg_2_length; /* Data segment 2 length. */ 1676 uint32_t dseg_3_address[2]; /* Data segment 3 address. */ 1677 uint32_t dseg_3_length; /* Data segment 3 length. */ 1678 uint32_t dseg_4_address[2]; /* Data segment 4 address. */ 1679 uint32_t dseg_4_length; /* Data segment 4 length. */ 1680 } cont_a64_entry_t; 1681 1682 #define PO_MODE_DIF_INSERT 0 1683 #define PO_MODE_DIF_REMOVE 1 1684 #define PO_MODE_DIF_PASS 2 1685 #define PO_MODE_DIF_REPLACE 3 1686 #define PO_MODE_DIF_TCP_CKSUM 6 1687 #define PO_ENABLE_INCR_GUARD_SEED BIT_3 1688 #define PO_DISABLE_GUARD_CHECK BIT_4 1689 #define PO_DISABLE_INCR_REF_TAG BIT_5 1690 #define PO_DIS_HEADER_MODE BIT_7 1691 #define PO_ENABLE_DIF_BUNDLING BIT_8 1692 #define PO_DIS_FRAME_MODE BIT_9 1693 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */ 1694 #define PO_DIS_VALD_APP_REF_ESC BIT_11 1695 1696 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */ 1697 #define PO_DIS_REF_TAG_REPL BIT_13 1698 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */ 1699 #define PO_DIS_REF_TAG_VALD BIT_15 1700 1701 /* 1702 * ISP queue - 64-Bit addressing, continuation crc entry structure definition. 1703 */ 1704 struct crc_context { 1705 uint32_t handle; /* System handle. */ 1706 __le32 ref_tag; 1707 __le16 app_tag; 1708 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/ 1709 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/ 1710 __le16 guard_seed; /* Initial Guard Seed */ 1711 __le16 prot_opts; /* Requested Data Protection Mode */ 1712 __le16 blk_size; /* Data size in bytes */ 1713 uint16_t runt_blk_guard; /* Guard value for runt block (tape 1714 * only) */ 1715 __le32 byte_count; /* Total byte count/ total data 1716 * transfer count */ 1717 union { 1718 struct { 1719 uint32_t reserved_1; 1720 uint16_t reserved_2; 1721 uint16_t reserved_3; 1722 uint32_t reserved_4; 1723 uint32_t data_address[2]; 1724 uint32_t data_length; 1725 uint32_t reserved_5[2]; 1726 uint32_t reserved_6; 1727 } nobundling; 1728 struct { 1729 __le32 dif_byte_count; /* Total DIF byte 1730 * count */ 1731 uint16_t reserved_1; 1732 __le16 dseg_count; /* Data segment count */ 1733 uint32_t reserved_2; 1734 uint32_t data_address[2]; 1735 uint32_t data_length; 1736 uint32_t dif_address[2]; 1737 uint32_t dif_length; /* Data segment 0 1738 * length */ 1739 } bundling; 1740 } u; 1741 1742 struct fcp_cmnd fcp_cmnd; 1743 dma_addr_t crc_ctx_dma; 1744 /* List of DMA context transfers */ 1745 struct list_head dsd_list; 1746 1747 /* This structure should not exceed 512 bytes */ 1748 }; 1749 1750 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun)) 1751 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun)) 1752 1753 /* 1754 * ISP queue - status entry structure definition. 1755 */ 1756 #define STATUS_TYPE 0x03 /* Status entry. */ 1757 typedef struct { 1758 uint8_t entry_type; /* Entry type. */ 1759 uint8_t entry_count; /* Entry count. */ 1760 uint8_t sys_define; /* System defined. */ 1761 uint8_t entry_status; /* Entry Status. */ 1762 uint32_t handle; /* System handle. */ 1763 uint16_t scsi_status; /* SCSI status. */ 1764 uint16_t comp_status; /* Completion status. */ 1765 uint16_t state_flags; /* State flags. */ 1766 uint16_t status_flags; /* Status flags. */ 1767 uint16_t rsp_info_len; /* Response Info Length. */ 1768 uint16_t req_sense_length; /* Request sense data length. */ 1769 uint32_t residual_length; /* Residual transfer length. */ 1770 uint8_t rsp_info[8]; /* FCP response information. */ 1771 uint8_t req_sense_data[32]; /* Request sense data. */ 1772 } sts_entry_t; 1773 1774 /* 1775 * Status entry entry status 1776 */ 1777 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */ 1778 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */ 1779 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */ 1780 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */ 1781 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */ 1782 #define RF_BUSY BIT_1 /* Busy */ 1783 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \ 1784 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY) 1785 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \ 1786 RF_INV_E_TYPE) 1787 1788 /* 1789 * Status entry SCSI status bit definitions. 1790 */ 1791 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/ 1792 #define SS_RESIDUAL_UNDER BIT_11 1793 #define SS_RESIDUAL_OVER BIT_10 1794 #define SS_SENSE_LEN_VALID BIT_9 1795 #define SS_RESPONSE_INFO_LEN_VALID BIT_8 1796 1797 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3) 1798 #define SS_BUSY_CONDITION BIT_3 1799 #define SS_CONDITION_MET BIT_2 1800 #define SS_CHECK_CONDITION BIT_1 1801 1802 /* 1803 * Status entry completion status 1804 */ 1805 #define CS_COMPLETE 0x0 /* No errors */ 1806 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ 1807 #define CS_DMA 0x2 /* A DMA direction error. */ 1808 #define CS_TRANSPORT 0x3 /* Transport error. */ 1809 #define CS_RESET 0x4 /* SCSI bus reset occurred */ 1810 #define CS_ABORTED 0x5 /* System aborted command. */ 1811 #define CS_TIMEOUT 0x6 /* Timeout error. */ 1812 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ 1813 #define CS_DIF_ERROR 0xC /* DIF error detected */ 1814 1815 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ 1816 #define CS_QUEUE_FULL 0x1C /* Queue Full. */ 1817 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */ 1818 /* (selection timeout) */ 1819 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */ 1820 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */ 1821 #define CS_PORT_BUSY 0x2B /* Port Busy */ 1822 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */ 1823 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request 1824 failure */ 1825 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ 1826 #define CS_UNKNOWN 0x81 /* Driver defined */ 1827 #define CS_RETRY 0x82 /* Driver defined */ 1828 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */ 1829 1830 #define CS_BIDIR_RD_OVERRUN 0x700 1831 #define CS_BIDIR_RD_WR_OVERRUN 0x707 1832 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715 1833 #define CS_BIDIR_RD_UNDERRUN 0x1500 1834 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507 1835 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515 1836 #define CS_BIDIR_DMA 0x200 1837 /* 1838 * Status entry status flags 1839 */ 1840 #define SF_ABTS_TERMINATED BIT_10 1841 #define SF_LOGOUT_SENT BIT_13 1842 1843 /* 1844 * ISP queue - status continuation entry structure definition. 1845 */ 1846 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */ 1847 typedef struct { 1848 uint8_t entry_type; /* Entry type. */ 1849 uint8_t entry_count; /* Entry count. */ 1850 uint8_t sys_define; /* System defined. */ 1851 uint8_t entry_status; /* Entry Status. */ 1852 uint8_t data[60]; /* data */ 1853 } sts_cont_entry_t; 1854 1855 /* 1856 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles) 1857 * structure definition. 1858 */ 1859 #define STATUS_TYPE_21 0x21 /* Status entry. */ 1860 typedef struct { 1861 uint8_t entry_type; /* Entry type. */ 1862 uint8_t entry_count; /* Entry count. */ 1863 uint8_t handle_count; /* Handle count. */ 1864 uint8_t entry_status; /* Entry Status. */ 1865 uint32_t handle[15]; /* System handles. */ 1866 } sts21_entry_t; 1867 1868 /* 1869 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles) 1870 * structure definition. 1871 */ 1872 #define STATUS_TYPE_22 0x22 /* Status entry. */ 1873 typedef struct { 1874 uint8_t entry_type; /* Entry type. */ 1875 uint8_t entry_count; /* Entry count. */ 1876 uint8_t handle_count; /* Handle count. */ 1877 uint8_t entry_status; /* Entry Status. */ 1878 uint16_t handle[30]; /* System handles. */ 1879 } sts22_entry_t; 1880 1881 /* 1882 * ISP queue - marker entry structure definition. 1883 */ 1884 #define MARKER_TYPE 0x04 /* Marker entry. */ 1885 typedef struct { 1886 uint8_t entry_type; /* Entry type. */ 1887 uint8_t entry_count; /* Entry count. */ 1888 uint8_t handle_count; /* Handle count. */ 1889 uint8_t entry_status; /* Entry Status. */ 1890 uint32_t sys_define_2; /* System defined. */ 1891 target_id_t target; /* SCSI ID */ 1892 uint8_t modifier; /* Modifier (7-0). */ 1893 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ 1894 #define MK_SYNC_ID 1 /* Synchronize ID */ 1895 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ 1896 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */ 1897 /* clear port changed, */ 1898 /* use sequence number. */ 1899 uint8_t reserved_1; 1900 uint16_t sequence_number; /* Sequence number of event */ 1901 uint16_t lun; /* SCSI LUN */ 1902 uint8_t reserved_2[48]; 1903 } mrk_entry_t; 1904 1905 /* 1906 * ISP queue - Management Server entry structure definition. 1907 */ 1908 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */ 1909 typedef struct { 1910 uint8_t entry_type; /* Entry type. */ 1911 uint8_t entry_count; /* Entry count. */ 1912 uint8_t handle_count; /* Handle count. */ 1913 uint8_t entry_status; /* Entry Status. */ 1914 uint32_t handle1; /* System handle. */ 1915 target_id_t loop_id; 1916 uint16_t status; 1917 uint16_t control_flags; /* Control flags. */ 1918 uint16_t reserved2; 1919 uint16_t timeout; 1920 uint16_t cmd_dsd_count; 1921 uint16_t total_dsd_count; 1922 uint8_t type; 1923 uint8_t r_ctl; 1924 uint16_t rx_id; 1925 uint16_t reserved3; 1926 uint32_t handle2; 1927 uint32_t rsp_bytecount; 1928 uint32_t req_bytecount; 1929 uint32_t dseg_req_address[2]; /* Data segment 0 address. */ 1930 uint32_t dseg_req_length; /* Data segment 0 length. */ 1931 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */ 1932 uint32_t dseg_rsp_length; /* Data segment 1 length. */ 1933 } ms_iocb_entry_t; 1934 1935 1936 /* 1937 * ISP queue - Mailbox Command entry structure definition. 1938 */ 1939 #define MBX_IOCB_TYPE 0x39 1940 struct mbx_entry { 1941 uint8_t entry_type; 1942 uint8_t entry_count; 1943 uint8_t sys_define1; 1944 /* Use sys_define1 for source type */ 1945 #define SOURCE_SCSI 0x00 1946 #define SOURCE_IP 0x01 1947 #define SOURCE_VI 0x02 1948 #define SOURCE_SCTP 0x03 1949 #define SOURCE_MP 0x04 1950 #define SOURCE_MPIOCTL 0x05 1951 #define SOURCE_ASYNC_IOCB 0x07 1952 1953 uint8_t entry_status; 1954 1955 uint32_t handle; 1956 target_id_t loop_id; 1957 1958 uint16_t status; 1959 uint16_t state_flags; 1960 uint16_t status_flags; 1961 1962 uint32_t sys_define2[2]; 1963 1964 uint16_t mb0; 1965 uint16_t mb1; 1966 uint16_t mb2; 1967 uint16_t mb3; 1968 uint16_t mb6; 1969 uint16_t mb7; 1970 uint16_t mb9; 1971 uint16_t mb10; 1972 uint32_t reserved_2[2]; 1973 uint8_t node_name[WWN_SIZE]; 1974 uint8_t port_name[WWN_SIZE]; 1975 }; 1976 1977 /* 1978 * ISP request and response queue entry sizes 1979 */ 1980 #define RESPONSE_ENTRY_SIZE (sizeof(response_t)) 1981 #define REQUEST_ENTRY_SIZE (sizeof(request_t)) 1982 1983 1984 /* 1985 * 24 bit port ID type definition. 1986 */ 1987 typedef union { 1988 uint32_t b24 : 24; 1989 1990 struct { 1991 #ifdef __BIG_ENDIAN 1992 uint8_t domain; 1993 uint8_t area; 1994 uint8_t al_pa; 1995 #elif defined(__LITTLE_ENDIAN) 1996 uint8_t al_pa; 1997 uint8_t area; 1998 uint8_t domain; 1999 #else 2000 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!" 2001 #endif 2002 uint8_t rsvd_1; 2003 } b; 2004 } port_id_t; 2005 #define INVALID_PORT_ID 0xFFFFFF 2006 2007 /* 2008 * Switch info gathering structure. 2009 */ 2010 typedef struct { 2011 port_id_t d_id; 2012 uint8_t node_name[WWN_SIZE]; 2013 uint8_t port_name[WWN_SIZE]; 2014 uint8_t fabric_port_name[WWN_SIZE]; 2015 uint16_t fp_speed; 2016 uint8_t fc4_type; 2017 } sw_info_t; 2018 2019 /* FCP-4 types */ 2020 #define FC4_TYPE_FCP_SCSI 0x08 2021 #define FC4_TYPE_OTHER 0x0 2022 #define FC4_TYPE_UNKNOWN 0xff 2023 2024 /* 2025 * Fibre channel port type. 2026 */ 2027 typedef enum { 2028 FCT_UNKNOWN, 2029 FCT_RSCN, 2030 FCT_SWITCH, 2031 FCT_BROADCAST, 2032 FCT_INITIATOR, 2033 FCT_TARGET 2034 } fc_port_type_t; 2035 2036 /* 2037 * Fibre channel port structure. 2038 */ 2039 typedef struct fc_port { 2040 struct list_head list; 2041 struct scsi_qla_host *vha; 2042 2043 uint8_t node_name[WWN_SIZE]; 2044 uint8_t port_name[WWN_SIZE]; 2045 port_id_t d_id; 2046 uint16_t loop_id; 2047 uint16_t old_loop_id; 2048 2049 uint16_t tgt_id; 2050 uint16_t old_tgt_id; 2051 2052 uint8_t fcp_prio; 2053 2054 uint8_t fabric_port_name[WWN_SIZE]; 2055 uint16_t fp_speed; 2056 2057 fc_port_type_t port_type; 2058 2059 atomic_t state; 2060 uint32_t flags; 2061 2062 int login_retry; 2063 2064 struct fc_rport *rport, *drport; 2065 u32 supported_classes; 2066 2067 uint8_t fc4_type; 2068 uint8_t scan_state; 2069 2070 unsigned long last_queue_full; 2071 unsigned long last_ramp_up; 2072 2073 uint16_t port_id; 2074 2075 unsigned long retry_delay_timestamp; 2076 struct qla_tgt_sess *tgt_session; 2077 } fc_port_t; 2078 2079 #include "qla_mr.h" 2080 2081 /* 2082 * Fibre channel port/lun states. 2083 */ 2084 #define FCS_UNCONFIGURED 1 2085 #define FCS_DEVICE_DEAD 2 2086 #define FCS_DEVICE_LOST 3 2087 #define FCS_ONLINE 4 2088 2089 static const char * const port_state_str[] = { 2090 "Unknown", 2091 "UNCONFIGURED", 2092 "DEAD", 2093 "LOST", 2094 "ONLINE" 2095 }; 2096 2097 /* 2098 * FC port flags. 2099 */ 2100 #define FCF_FABRIC_DEVICE BIT_0 2101 #define FCF_LOGIN_NEEDED BIT_1 2102 #define FCF_FCP2_DEVICE BIT_2 2103 #define FCF_ASYNC_SENT BIT_3 2104 #define FCF_CONF_COMP_SUPPORTED BIT_4 2105 2106 /* No loop ID flag. */ 2107 #define FC_NO_LOOP_ID 0x1000 2108 2109 /* 2110 * FC-CT interface 2111 * 2112 * NOTE: All structures are big-endian in form. 2113 */ 2114 2115 #define CT_REJECT_RESPONSE 0x8001 2116 #define CT_ACCEPT_RESPONSE 0x8002 2117 #define CT_REASON_INVALID_COMMAND_CODE 0x01 2118 #define CT_REASON_CANNOT_PERFORM 0x09 2119 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b 2120 #define CT_EXPL_ALREADY_REGISTERED 0x10 2121 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11 2122 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12 2123 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13 2124 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14 2125 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15 2126 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16 2127 #define CT_EXPL_HBA_NOT_REGISTERED 0x17 2128 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20 2129 #define CT_EXPL_PORT_NOT_REGISTERED 0x21 2130 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22 2131 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23 2132 2133 #define NS_N_PORT_TYPE 0x01 2134 #define NS_NL_PORT_TYPE 0x02 2135 #define NS_NX_PORT_TYPE 0x7F 2136 2137 #define GA_NXT_CMD 0x100 2138 #define GA_NXT_REQ_SIZE (16 + 4) 2139 #define GA_NXT_RSP_SIZE (16 + 620) 2140 2141 #define GID_PT_CMD 0x1A1 2142 #define GID_PT_REQ_SIZE (16 + 4) 2143 2144 #define GPN_ID_CMD 0x112 2145 #define GPN_ID_REQ_SIZE (16 + 4) 2146 #define GPN_ID_RSP_SIZE (16 + 8) 2147 2148 #define GNN_ID_CMD 0x113 2149 #define GNN_ID_REQ_SIZE (16 + 4) 2150 #define GNN_ID_RSP_SIZE (16 + 8) 2151 2152 #define GFT_ID_CMD 0x117 2153 #define GFT_ID_REQ_SIZE (16 + 4) 2154 #define GFT_ID_RSP_SIZE (16 + 32) 2155 2156 #define RFT_ID_CMD 0x217 2157 #define RFT_ID_REQ_SIZE (16 + 4 + 32) 2158 #define RFT_ID_RSP_SIZE 16 2159 2160 #define RFF_ID_CMD 0x21F 2161 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1) 2162 #define RFF_ID_RSP_SIZE 16 2163 2164 #define RNN_ID_CMD 0x213 2165 #define RNN_ID_REQ_SIZE (16 + 4 + 8) 2166 #define RNN_ID_RSP_SIZE 16 2167 2168 #define RSNN_NN_CMD 0x239 2169 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255) 2170 #define RSNN_NN_RSP_SIZE 16 2171 2172 #define GFPN_ID_CMD 0x11C 2173 #define GFPN_ID_REQ_SIZE (16 + 4) 2174 #define GFPN_ID_RSP_SIZE (16 + 8) 2175 2176 #define GPSC_CMD 0x127 2177 #define GPSC_REQ_SIZE (16 + 8) 2178 #define GPSC_RSP_SIZE (16 + 2 + 2) 2179 2180 #define GFF_ID_CMD 0x011F 2181 #define GFF_ID_REQ_SIZE (16 + 4) 2182 #define GFF_ID_RSP_SIZE (16 + 128) 2183 2184 /* 2185 * HBA attribute types. 2186 */ 2187 #define FDMI_HBA_ATTR_COUNT 9 2188 #define FDMIV2_HBA_ATTR_COUNT 17 2189 #define FDMI_HBA_NODE_NAME 0x1 2190 #define FDMI_HBA_MANUFACTURER 0x2 2191 #define FDMI_HBA_SERIAL_NUMBER 0x3 2192 #define FDMI_HBA_MODEL 0x4 2193 #define FDMI_HBA_MODEL_DESCRIPTION 0x5 2194 #define FDMI_HBA_HARDWARE_VERSION 0x6 2195 #define FDMI_HBA_DRIVER_VERSION 0x7 2196 #define FDMI_HBA_OPTION_ROM_VERSION 0x8 2197 #define FDMI_HBA_FIRMWARE_VERSION 0x9 2198 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa 2199 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb 2200 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc 2201 #define FDMI_HBA_VENDOR_ID 0xd 2202 #define FDMI_HBA_NUM_PORTS 0xe 2203 #define FDMI_HBA_FABRIC_NAME 0xf 2204 #define FDMI_HBA_BOOT_BIOS_NAME 0x10 2205 #define FDMI_HBA_TYPE_VENDOR_IDENTIFIER 0xe0 2206 2207 struct ct_fdmi_hba_attr { 2208 uint16_t type; 2209 uint16_t len; 2210 union { 2211 uint8_t node_name[WWN_SIZE]; 2212 uint8_t manufacturer[64]; 2213 uint8_t serial_num[32]; 2214 uint8_t model[16+1]; 2215 uint8_t model_desc[80]; 2216 uint8_t hw_version[32]; 2217 uint8_t driver_version[32]; 2218 uint8_t orom_version[16]; 2219 uint8_t fw_version[32]; 2220 uint8_t os_version[128]; 2221 uint32_t max_ct_len; 2222 } a; 2223 }; 2224 2225 struct ct_fdmi_hba_attributes { 2226 uint32_t count; 2227 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT]; 2228 }; 2229 2230 struct ct_fdmiv2_hba_attr { 2231 uint16_t type; 2232 uint16_t len; 2233 union { 2234 uint8_t node_name[WWN_SIZE]; 2235 uint8_t manufacturer[64]; 2236 uint8_t serial_num[32]; 2237 uint8_t model[16+1]; 2238 uint8_t model_desc[80]; 2239 uint8_t hw_version[16]; 2240 uint8_t driver_version[32]; 2241 uint8_t orom_version[16]; 2242 uint8_t fw_version[32]; 2243 uint8_t os_version[128]; 2244 uint32_t max_ct_len; 2245 uint8_t sym_name[256]; 2246 uint32_t vendor_id; 2247 uint32_t num_ports; 2248 uint8_t fabric_name[WWN_SIZE]; 2249 uint8_t bios_name[32]; 2250 uint8_t vendor_indentifer[8]; 2251 } a; 2252 }; 2253 2254 struct ct_fdmiv2_hba_attributes { 2255 uint32_t count; 2256 struct ct_fdmiv2_hba_attr entry[FDMIV2_HBA_ATTR_COUNT]; 2257 }; 2258 2259 /* 2260 * Port attribute types. 2261 */ 2262 #define FDMI_PORT_ATTR_COUNT 6 2263 #define FDMIV2_PORT_ATTR_COUNT 16 2264 #define FDMI_PORT_FC4_TYPES 0x1 2265 #define FDMI_PORT_SUPPORT_SPEED 0x2 2266 #define FDMI_PORT_CURRENT_SPEED 0x3 2267 #define FDMI_PORT_MAX_FRAME_SIZE 0x4 2268 #define FDMI_PORT_OS_DEVICE_NAME 0x5 2269 #define FDMI_PORT_HOST_NAME 0x6 2270 #define FDMI_PORT_NODE_NAME 0x7 2271 #define FDMI_PORT_NAME 0x8 2272 #define FDMI_PORT_SYM_NAME 0x9 2273 #define FDMI_PORT_TYPE 0xa 2274 #define FDMI_PORT_SUPP_COS 0xb 2275 #define FDMI_PORT_FABRIC_NAME 0xc 2276 #define FDMI_PORT_FC4_TYPE 0xd 2277 #define FDMI_PORT_STATE 0x101 2278 #define FDMI_PORT_COUNT 0x102 2279 #define FDMI_PORT_ID 0x103 2280 2281 #define FDMI_PORT_SPEED_1GB 0x1 2282 #define FDMI_PORT_SPEED_2GB 0x2 2283 #define FDMI_PORT_SPEED_10GB 0x4 2284 #define FDMI_PORT_SPEED_4GB 0x8 2285 #define FDMI_PORT_SPEED_8GB 0x10 2286 #define FDMI_PORT_SPEED_16GB 0x20 2287 #define FDMI_PORT_SPEED_32GB 0x40 2288 #define FDMI_PORT_SPEED_UNKNOWN 0x8000 2289 2290 #define FC_CLASS_2 0x04 2291 #define FC_CLASS_3 0x08 2292 #define FC_CLASS_2_3 0x0C 2293 2294 struct ct_fdmiv2_port_attr { 2295 uint16_t type; 2296 uint16_t len; 2297 union { 2298 uint8_t fc4_types[32]; 2299 uint32_t sup_speed; 2300 uint32_t cur_speed; 2301 uint32_t max_frame_size; 2302 uint8_t os_dev_name[32]; 2303 uint8_t host_name[256]; 2304 uint8_t node_name[WWN_SIZE]; 2305 uint8_t port_name[WWN_SIZE]; 2306 uint8_t port_sym_name[128]; 2307 uint32_t port_type; 2308 uint32_t port_supported_cos; 2309 uint8_t fabric_name[WWN_SIZE]; 2310 uint8_t port_fc4_type[32]; 2311 uint32_t port_state; 2312 uint32_t num_ports; 2313 uint32_t port_id; 2314 } a; 2315 }; 2316 2317 /* 2318 * Port Attribute Block. 2319 */ 2320 struct ct_fdmiv2_port_attributes { 2321 uint32_t count; 2322 struct ct_fdmiv2_port_attr entry[FDMIV2_PORT_ATTR_COUNT]; 2323 }; 2324 2325 struct ct_fdmi_port_attr { 2326 uint16_t type; 2327 uint16_t len; 2328 union { 2329 uint8_t fc4_types[32]; 2330 uint32_t sup_speed; 2331 uint32_t cur_speed; 2332 uint32_t max_frame_size; 2333 uint8_t os_dev_name[32]; 2334 uint8_t host_name[256]; 2335 } a; 2336 }; 2337 2338 struct ct_fdmi_port_attributes { 2339 uint32_t count; 2340 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT]; 2341 }; 2342 2343 /* FDMI definitions. */ 2344 #define GRHL_CMD 0x100 2345 #define GHAT_CMD 0x101 2346 #define GRPL_CMD 0x102 2347 #define GPAT_CMD 0x110 2348 2349 #define RHBA_CMD 0x200 2350 #define RHBA_RSP_SIZE 16 2351 2352 #define RHAT_CMD 0x201 2353 #define RPRT_CMD 0x210 2354 2355 #define RPA_CMD 0x211 2356 #define RPA_RSP_SIZE 16 2357 2358 #define DHBA_CMD 0x300 2359 #define DHBA_REQ_SIZE (16 + 8) 2360 #define DHBA_RSP_SIZE 16 2361 2362 #define DHAT_CMD 0x301 2363 #define DPRT_CMD 0x310 2364 #define DPA_CMD 0x311 2365 2366 /* CT command header -- request/response common fields */ 2367 struct ct_cmd_hdr { 2368 uint8_t revision; 2369 uint8_t in_id[3]; 2370 uint8_t gs_type; 2371 uint8_t gs_subtype; 2372 uint8_t options; 2373 uint8_t reserved; 2374 }; 2375 2376 /* CT command request */ 2377 struct ct_sns_req { 2378 struct ct_cmd_hdr header; 2379 uint16_t command; 2380 uint16_t max_rsp_size; 2381 uint8_t fragment_id; 2382 uint8_t reserved[3]; 2383 2384 union { 2385 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */ 2386 struct { 2387 uint8_t reserved; 2388 uint8_t port_id[3]; 2389 } port_id; 2390 2391 struct { 2392 uint8_t port_type; 2393 uint8_t domain; 2394 uint8_t area; 2395 uint8_t reserved; 2396 } gid_pt; 2397 2398 struct { 2399 uint8_t reserved; 2400 uint8_t port_id[3]; 2401 uint8_t fc4_types[32]; 2402 } rft_id; 2403 2404 struct { 2405 uint8_t reserved; 2406 uint8_t port_id[3]; 2407 uint16_t reserved2; 2408 uint8_t fc4_feature; 2409 uint8_t fc4_type; 2410 } rff_id; 2411 2412 struct { 2413 uint8_t reserved; 2414 uint8_t port_id[3]; 2415 uint8_t node_name[8]; 2416 } rnn_id; 2417 2418 struct { 2419 uint8_t node_name[8]; 2420 uint8_t name_len; 2421 uint8_t sym_node_name[255]; 2422 } rsnn_nn; 2423 2424 struct { 2425 uint8_t hba_indentifier[8]; 2426 } ghat; 2427 2428 struct { 2429 uint8_t hba_identifier[8]; 2430 uint32_t entry_count; 2431 uint8_t port_name[8]; 2432 struct ct_fdmi_hba_attributes attrs; 2433 } rhba; 2434 2435 struct { 2436 uint8_t hba_identifier[8]; 2437 uint32_t entry_count; 2438 uint8_t port_name[8]; 2439 struct ct_fdmiv2_hba_attributes attrs; 2440 } rhba2; 2441 2442 struct { 2443 uint8_t hba_identifier[8]; 2444 struct ct_fdmi_hba_attributes attrs; 2445 } rhat; 2446 2447 struct { 2448 uint8_t port_name[8]; 2449 struct ct_fdmi_port_attributes attrs; 2450 } rpa; 2451 2452 struct { 2453 uint8_t port_name[8]; 2454 struct ct_fdmiv2_port_attributes attrs; 2455 } rpa2; 2456 2457 struct { 2458 uint8_t port_name[8]; 2459 } dhba; 2460 2461 struct { 2462 uint8_t port_name[8]; 2463 } dhat; 2464 2465 struct { 2466 uint8_t port_name[8]; 2467 } dprt; 2468 2469 struct { 2470 uint8_t port_name[8]; 2471 } dpa; 2472 2473 struct { 2474 uint8_t port_name[8]; 2475 } gpsc; 2476 2477 struct { 2478 uint8_t reserved; 2479 uint8_t port_name[3]; 2480 } gff_id; 2481 } req; 2482 }; 2483 2484 /* CT command response header */ 2485 struct ct_rsp_hdr { 2486 struct ct_cmd_hdr header; 2487 uint16_t response; 2488 uint16_t residual; 2489 uint8_t fragment_id; 2490 uint8_t reason_code; 2491 uint8_t explanation_code; 2492 uint8_t vendor_unique; 2493 }; 2494 2495 struct ct_sns_gid_pt_data { 2496 uint8_t control_byte; 2497 uint8_t port_id[3]; 2498 }; 2499 2500 struct ct_sns_rsp { 2501 struct ct_rsp_hdr header; 2502 2503 union { 2504 struct { 2505 uint8_t port_type; 2506 uint8_t port_id[3]; 2507 uint8_t port_name[8]; 2508 uint8_t sym_port_name_len; 2509 uint8_t sym_port_name[255]; 2510 uint8_t node_name[8]; 2511 uint8_t sym_node_name_len; 2512 uint8_t sym_node_name[255]; 2513 uint8_t init_proc_assoc[8]; 2514 uint8_t node_ip_addr[16]; 2515 uint8_t class_of_service[4]; 2516 uint8_t fc4_types[32]; 2517 uint8_t ip_address[16]; 2518 uint8_t fabric_port_name[8]; 2519 uint8_t reserved; 2520 uint8_t hard_address[3]; 2521 } ga_nxt; 2522 2523 struct { 2524 /* Assume the largest number of targets for the union */ 2525 struct ct_sns_gid_pt_data 2526 entries[MAX_FIBRE_DEVICES_MAX]; 2527 } gid_pt; 2528 2529 struct { 2530 uint8_t port_name[8]; 2531 } gpn_id; 2532 2533 struct { 2534 uint8_t node_name[8]; 2535 } gnn_id; 2536 2537 struct { 2538 uint8_t fc4_types[32]; 2539 } gft_id; 2540 2541 struct { 2542 uint32_t entry_count; 2543 uint8_t port_name[8]; 2544 struct ct_fdmi_hba_attributes attrs; 2545 } ghat; 2546 2547 struct { 2548 uint8_t port_name[8]; 2549 } gfpn_id; 2550 2551 struct { 2552 uint16_t speeds; 2553 uint16_t speed; 2554 } gpsc; 2555 2556 #define GFF_FCP_SCSI_OFFSET 7 2557 struct { 2558 uint8_t fc4_features[128]; 2559 } gff_id; 2560 } rsp; 2561 }; 2562 2563 struct ct_sns_pkt { 2564 union { 2565 struct ct_sns_req req; 2566 struct ct_sns_rsp rsp; 2567 } p; 2568 }; 2569 2570 /* 2571 * SNS command structures -- for 2200 compatibility. 2572 */ 2573 #define RFT_ID_SNS_SCMD_LEN 22 2574 #define RFT_ID_SNS_CMD_SIZE 60 2575 #define RFT_ID_SNS_DATA_SIZE 16 2576 2577 #define RNN_ID_SNS_SCMD_LEN 10 2578 #define RNN_ID_SNS_CMD_SIZE 36 2579 #define RNN_ID_SNS_DATA_SIZE 16 2580 2581 #define GA_NXT_SNS_SCMD_LEN 6 2582 #define GA_NXT_SNS_CMD_SIZE 28 2583 #define GA_NXT_SNS_DATA_SIZE (620 + 16) 2584 2585 #define GID_PT_SNS_SCMD_LEN 6 2586 #define GID_PT_SNS_CMD_SIZE 28 2587 /* 2588 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older 2589 * adapters. 2590 */ 2591 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16) 2592 2593 #define GPN_ID_SNS_SCMD_LEN 6 2594 #define GPN_ID_SNS_CMD_SIZE 28 2595 #define GPN_ID_SNS_DATA_SIZE (8 + 16) 2596 2597 #define GNN_ID_SNS_SCMD_LEN 6 2598 #define GNN_ID_SNS_CMD_SIZE 28 2599 #define GNN_ID_SNS_DATA_SIZE (8 + 16) 2600 2601 struct sns_cmd_pkt { 2602 union { 2603 struct { 2604 uint16_t buffer_length; 2605 uint16_t reserved_1; 2606 uint32_t buffer_address[2]; 2607 uint16_t subcommand_length; 2608 uint16_t reserved_2; 2609 uint16_t subcommand; 2610 uint16_t size; 2611 uint32_t reserved_3; 2612 uint8_t param[36]; 2613 } cmd; 2614 2615 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE]; 2616 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE]; 2617 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE]; 2618 uint8_t gid_data[GID_PT_SNS_DATA_SIZE]; 2619 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE]; 2620 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE]; 2621 } p; 2622 }; 2623 2624 struct fw_blob { 2625 char *name; 2626 uint32_t segs[4]; 2627 const struct firmware *fw; 2628 }; 2629 2630 /* Return data from MBC_GET_ID_LIST call. */ 2631 struct gid_list_info { 2632 uint8_t al_pa; 2633 uint8_t area; 2634 uint8_t domain; 2635 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */ 2636 uint16_t loop_id; /* ISP23XX -- 6 bytes. */ 2637 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */ 2638 }; 2639 2640 /* NPIV */ 2641 typedef struct vport_info { 2642 uint8_t port_name[WWN_SIZE]; 2643 uint8_t node_name[WWN_SIZE]; 2644 int vp_id; 2645 uint16_t loop_id; 2646 unsigned long host_no; 2647 uint8_t port_id[3]; 2648 int loop_state; 2649 } vport_info_t; 2650 2651 typedef struct vport_params { 2652 uint8_t port_name[WWN_SIZE]; 2653 uint8_t node_name[WWN_SIZE]; 2654 uint32_t options; 2655 #define VP_OPTS_RETRY_ENABLE BIT_0 2656 #define VP_OPTS_VP_DISABLE BIT_1 2657 } vport_params_t; 2658 2659 /* NPIV - return codes of VP create and modify */ 2660 #define VP_RET_CODE_OK 0 2661 #define VP_RET_CODE_FATAL 1 2662 #define VP_RET_CODE_WRONG_ID 2 2663 #define VP_RET_CODE_WWPN 3 2664 #define VP_RET_CODE_RESOURCES 4 2665 #define VP_RET_CODE_NO_MEM 5 2666 #define VP_RET_CODE_NOT_FOUND 6 2667 2668 struct qla_hw_data; 2669 struct rsp_que; 2670 /* 2671 * ISP operations 2672 */ 2673 struct isp_operations { 2674 2675 int (*pci_config) (struct scsi_qla_host *); 2676 void (*reset_chip) (struct scsi_qla_host *); 2677 int (*chip_diag) (struct scsi_qla_host *); 2678 void (*config_rings) (struct scsi_qla_host *); 2679 void (*reset_adapter) (struct scsi_qla_host *); 2680 int (*nvram_config) (struct scsi_qla_host *); 2681 void (*update_fw_options) (struct scsi_qla_host *); 2682 int (*load_risc) (struct scsi_qla_host *, uint32_t *); 2683 2684 char * (*pci_info_str) (struct scsi_qla_host *, char *); 2685 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t); 2686 2687 irq_handler_t intr_handler; 2688 void (*enable_intrs) (struct qla_hw_data *); 2689 void (*disable_intrs) (struct qla_hw_data *); 2690 2691 int (*abort_command) (srb_t *); 2692 int (*target_reset) (struct fc_port *, uint64_t, int); 2693 int (*lun_reset) (struct fc_port *, uint64_t, int); 2694 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t, 2695 uint8_t, uint8_t, uint16_t *, uint8_t); 2696 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t, 2697 uint8_t, uint8_t); 2698 2699 uint16_t (*calc_req_entries) (uint16_t); 2700 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t); 2701 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t); 2702 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t, 2703 uint32_t); 2704 2705 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *, 2706 uint32_t, uint32_t); 2707 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t, 2708 uint32_t); 2709 2710 void (*fw_dump) (struct scsi_qla_host *, int); 2711 2712 int (*beacon_on) (struct scsi_qla_host *); 2713 int (*beacon_off) (struct scsi_qla_host *); 2714 void (*beacon_blink) (struct scsi_qla_host *); 2715 2716 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *, 2717 uint32_t, uint32_t); 2718 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t, 2719 uint32_t); 2720 2721 int (*get_flash_version) (struct scsi_qla_host *, void *); 2722 int (*start_scsi) (srb_t *); 2723 int (*abort_isp) (struct scsi_qla_host *); 2724 int (*iospace_config)(struct qla_hw_data*); 2725 int (*initialize_adapter)(struct scsi_qla_host *); 2726 }; 2727 2728 /* MSI-X Support *************************************************************/ 2729 2730 #define QLA_MSIX_CHIP_REV_24XX 3 2731 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7) 2732 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1) 2733 2734 #define QLA_MSIX_DEFAULT 0x00 2735 #define QLA_MSIX_RSP_Q 0x01 2736 2737 #define QLA_MIDX_DEFAULT 0 2738 #define QLA_MIDX_RSP_Q 1 2739 #define QLA_PCI_MSIX_CONTROL 0xa2 2740 #define QLA_83XX_PCI_MSIX_CONTROL 0x92 2741 2742 struct scsi_qla_host; 2743 2744 2745 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */ 2746 2747 struct qla_msix_entry { 2748 int have_irq; 2749 uint32_t vector; 2750 uint16_t entry; 2751 struct rsp_que *rsp; 2752 struct irq_affinity_notify irq_notify; 2753 int cpuid; 2754 }; 2755 2756 #define WATCH_INTERVAL 1 /* number of seconds */ 2757 2758 /* Work events. */ 2759 enum qla_work_type { 2760 QLA_EVT_AEN, 2761 QLA_EVT_IDC_ACK, 2762 QLA_EVT_ASYNC_LOGIN, 2763 QLA_EVT_ASYNC_LOGIN_DONE, 2764 QLA_EVT_ASYNC_LOGOUT, 2765 QLA_EVT_ASYNC_LOGOUT_DONE, 2766 QLA_EVT_ASYNC_ADISC, 2767 QLA_EVT_ASYNC_ADISC_DONE, 2768 QLA_EVT_UEVENT, 2769 QLA_EVT_AENFX, 2770 }; 2771 2772 2773 struct qla_work_evt { 2774 struct list_head list; 2775 enum qla_work_type type; 2776 u32 flags; 2777 #define QLA_EVT_FLAG_FREE 0x1 2778 2779 union { 2780 struct { 2781 enum fc_host_event_code code; 2782 u32 data; 2783 } aen; 2784 struct { 2785 #define QLA_IDC_ACK_REGS 7 2786 uint16_t mb[QLA_IDC_ACK_REGS]; 2787 } idc_ack; 2788 struct { 2789 struct fc_port *fcport; 2790 #define QLA_LOGIO_LOGIN_RETRIED BIT_0 2791 u16 data[2]; 2792 } logio; 2793 struct { 2794 u32 code; 2795 #define QLA_UEVENT_CODE_FW_DUMP 0 2796 } uevent; 2797 struct { 2798 uint32_t evtcode; 2799 uint32_t mbx[8]; 2800 uint32_t count; 2801 } aenfx; 2802 struct { 2803 srb_t *sp; 2804 } iosb; 2805 } u; 2806 }; 2807 2808 struct qla_chip_state_84xx { 2809 struct list_head list; 2810 struct kref kref; 2811 2812 void *bus; 2813 spinlock_t access_lock; 2814 struct mutex fw_update_mutex; 2815 uint32_t fw_update; 2816 uint32_t op_fw_version; 2817 uint32_t op_fw_size; 2818 uint32_t op_fw_seq_size; 2819 uint32_t diag_fw_version; 2820 uint32_t gold_fw_version; 2821 }; 2822 2823 struct qla_statistics { 2824 uint32_t total_isp_aborts; 2825 uint64_t input_bytes; 2826 uint64_t output_bytes; 2827 uint64_t input_requests; 2828 uint64_t output_requests; 2829 uint32_t control_requests; 2830 2831 uint64_t jiffies_at_last_reset; 2832 uint32_t stat_max_pend_cmds; 2833 uint32_t stat_max_qfull_cmds_alloc; 2834 uint32_t stat_max_qfull_cmds_dropped; 2835 }; 2836 2837 struct bidi_statistics { 2838 unsigned long long io_count; 2839 unsigned long long transfer_bytes; 2840 }; 2841 2842 /* Multi queue support */ 2843 #define MBC_INITIALIZE_MULTIQ 0x1f 2844 #define QLA_QUE_PAGE 0X1000 2845 #define QLA_MQ_SIZE 32 2846 #define QLA_MAX_QUEUES 256 2847 #define ISP_QUE_REG(ha, id) \ 2848 ((ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ? \ 2849 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\ 2850 ((void __iomem *)ha->iobase)) 2851 #define QLA_REQ_QUE_ID(tag) \ 2852 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0) 2853 #define QLA_DEFAULT_QUE_QOS 5 2854 #define QLA_PRECONFIG_VPORTS 32 2855 #define QLA_MAX_VPORTS_QLA24XX 128 2856 #define QLA_MAX_VPORTS_QLA25XX 256 2857 /* Response queue data structure */ 2858 struct rsp_que { 2859 dma_addr_t dma; 2860 response_t *ring; 2861 response_t *ring_ptr; 2862 uint32_t __iomem *rsp_q_in; /* FWI2-capable only. */ 2863 uint32_t __iomem *rsp_q_out; 2864 uint16_t ring_index; 2865 uint16_t out_ptr; 2866 uint16_t *in_ptr; /* queue shadow in index */ 2867 uint16_t length; 2868 uint16_t options; 2869 uint16_t rid; 2870 uint16_t id; 2871 uint16_t vp_idx; 2872 struct qla_hw_data *hw; 2873 struct qla_msix_entry *msix; 2874 struct req_que *req; 2875 srb_t *status_srb; /* status continuation entry */ 2876 struct work_struct q_work; 2877 2878 dma_addr_t dma_fx00; 2879 response_t *ring_fx00; 2880 uint16_t length_fx00; 2881 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE]; 2882 }; 2883 2884 /* Request queue data structure */ 2885 struct req_que { 2886 dma_addr_t dma; 2887 request_t *ring; 2888 request_t *ring_ptr; 2889 uint32_t __iomem *req_q_in; /* FWI2-capable only. */ 2890 uint32_t __iomem *req_q_out; 2891 uint16_t ring_index; 2892 uint16_t in_ptr; 2893 uint16_t *out_ptr; /* queue shadow out index */ 2894 uint16_t cnt; 2895 uint16_t length; 2896 uint16_t options; 2897 uint16_t rid; 2898 uint16_t id; 2899 uint16_t qos; 2900 uint16_t vp_idx; 2901 struct rsp_que *rsp; 2902 srb_t **outstanding_cmds; 2903 uint32_t current_outstanding_cmd; 2904 uint16_t num_outstanding_cmds; 2905 int max_q_depth; 2906 2907 dma_addr_t dma_fx00; 2908 request_t *ring_fx00; 2909 uint16_t length_fx00; 2910 uint8_t req_pkt[REQUEST_ENTRY_SIZE]; 2911 }; 2912 2913 /* Place holder for FW buffer parameters */ 2914 struct qlfc_fw { 2915 void *fw_buf; 2916 dma_addr_t fw_dma; 2917 uint32_t len; 2918 }; 2919 2920 struct scsi_qlt_host { 2921 void *target_lport_ptr; 2922 struct mutex tgt_mutex; 2923 struct mutex tgt_host_action_mutex; 2924 struct qla_tgt *qla_tgt; 2925 }; 2926 2927 struct qlt_hw_data { 2928 /* Protected by hw lock */ 2929 uint32_t enable_class_2:1; 2930 uint32_t enable_explicit_conf:1; 2931 uint32_t ini_mode_force_reverse:1; 2932 uint32_t node_name_set:1; 2933 2934 dma_addr_t atio_dma; /* Physical address. */ 2935 struct atio *atio_ring; /* Base virtual address */ 2936 struct atio *atio_ring_ptr; /* Current address. */ 2937 uint16_t atio_ring_index; /* Current index. */ 2938 uint16_t atio_q_length; 2939 uint32_t __iomem *atio_q_in; 2940 uint32_t __iomem *atio_q_out; 2941 2942 struct qla_tgt_func_tmpl *tgt_ops; 2943 struct qla_tgt_cmd *cmds[DEFAULT_OUTSTANDING_COMMANDS]; 2944 uint16_t current_handle; 2945 2946 struct qla_tgt_vp_map *tgt_vp_map; 2947 2948 int saved_set; 2949 uint16_t saved_exchange_count; 2950 uint32_t saved_firmware_options_1; 2951 uint32_t saved_firmware_options_2; 2952 uint32_t saved_firmware_options_3; 2953 uint8_t saved_firmware_options[2]; 2954 uint8_t saved_add_firmware_options[2]; 2955 2956 uint8_t tgt_node_name[WWN_SIZE]; 2957 2958 struct dentry *dfs_tgt_sess; 2959 struct list_head q_full_list; 2960 uint32_t num_pend_cmds; 2961 uint32_t num_qfull_cmds_alloc; 2962 uint32_t num_qfull_cmds_dropped; 2963 spinlock_t q_full_lock; 2964 uint32_t leak_exchg_thresh_hold; 2965 spinlock_t sess_lock; 2966 int rspq_vector_cpuid; 2967 spinlock_t atio_lock ____cacheline_aligned; 2968 }; 2969 2970 #define MAX_QFULL_CMDS_ALLOC 8192 2971 #define Q_FULL_THRESH_HOLD_PERCENT 90 2972 #define Q_FULL_THRESH_HOLD(ha) \ 2973 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT) 2974 2975 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */ 2976 2977 /* 2978 * Qlogic host adapter specific data structure. 2979 */ 2980 struct qla_hw_data { 2981 struct pci_dev *pdev; 2982 /* SRB cache. */ 2983 #define SRB_MIN_REQ 128 2984 mempool_t *srb_mempool; 2985 2986 volatile struct { 2987 uint32_t mbox_int :1; 2988 uint32_t mbox_busy :1; 2989 uint32_t disable_risc_code_load :1; 2990 uint32_t enable_64bit_addressing :1; 2991 uint32_t enable_lip_reset :1; 2992 uint32_t enable_target_reset :1; 2993 uint32_t enable_lip_full_login :1; 2994 uint32_t enable_led_scheme :1; 2995 2996 uint32_t msi_enabled :1; 2997 uint32_t msix_enabled :1; 2998 uint32_t disable_serdes :1; 2999 uint32_t gpsc_supported :1; 3000 uint32_t npiv_supported :1; 3001 uint32_t pci_channel_io_perm_failure :1; 3002 uint32_t fce_enabled :1; 3003 uint32_t fac_supported :1; 3004 3005 uint32_t chip_reset_done :1; 3006 uint32_t running_gold_fw :1; 3007 uint32_t eeh_busy :1; 3008 uint32_t cpu_affinity_enabled :1; 3009 uint32_t disable_msix_handshake :1; 3010 uint32_t fcp_prio_enabled :1; 3011 uint32_t isp82xx_fw_hung:1; 3012 uint32_t nic_core_hung:1; 3013 3014 uint32_t quiesce_owner:1; 3015 uint32_t nic_core_reset_hdlr_active:1; 3016 uint32_t nic_core_reset_owner:1; 3017 uint32_t isp82xx_no_md_cap:1; 3018 uint32_t host_shutting_down:1; 3019 uint32_t idc_compl_status:1; 3020 uint32_t mr_reset_hdlr_active:1; 3021 uint32_t mr_intr_valid:1; 3022 3023 uint32_t dport_enabled:1; 3024 uint32_t fawwpn_enabled:1; 3025 uint32_t exlogins_enabled:1; 3026 uint32_t exchoffld_enabled:1; 3027 /* 35 bits */ 3028 } flags; 3029 3030 /* This spinlock is used to protect "io transactions", you must 3031 * acquire it before doing any IO to the card, eg with RD_REG*() and 3032 * WRT_REG*() for the duration of your entire commandtransaction. 3033 * 3034 * This spinlock is of lower priority than the io request lock. 3035 */ 3036 3037 spinlock_t hardware_lock ____cacheline_aligned; 3038 int bars; 3039 int mem_only; 3040 device_reg_t *iobase; /* Base I/O address */ 3041 resource_size_t pio_address; 3042 3043 #define MIN_IOBASE_LEN 0x100 3044 dma_addr_t bar0_hdl; 3045 3046 void __iomem *cregbase; 3047 dma_addr_t bar2_hdl; 3048 #define BAR0_LEN_FX00 (1024 * 1024) 3049 #define BAR2_LEN_FX00 (128 * 1024) 3050 3051 uint32_t rqstq_intr_code; 3052 uint32_t mbx_intr_code; 3053 uint32_t req_que_len; 3054 uint32_t rsp_que_len; 3055 uint32_t req_que_off; 3056 uint32_t rsp_que_off; 3057 3058 /* Multi queue data structs */ 3059 device_reg_t *mqiobase; 3060 device_reg_t *msixbase; 3061 uint16_t msix_count; 3062 uint8_t mqenable; 3063 struct req_que **req_q_map; 3064 struct rsp_que **rsp_q_map; 3065 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3066 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)]; 3067 uint8_t max_req_queues; 3068 uint8_t max_rsp_queues; 3069 struct qla_npiv_entry *npiv_info; 3070 uint16_t nvram_npiv_size; 3071 3072 uint16_t switch_cap; 3073 #define FLOGI_SEQ_DEL BIT_8 3074 #define FLOGI_MID_SUPPORT BIT_10 3075 #define FLOGI_VSAN_SUPPORT BIT_12 3076 #define FLOGI_SP_SUPPORT BIT_13 3077 3078 uint8_t port_no; /* Physical port of adapter */ 3079 3080 /* Timeout timers. */ 3081 uint8_t loop_down_abort_time; /* port down timer */ 3082 atomic_t loop_down_timer; /* loop down timer */ 3083 uint8_t link_down_timeout; /* link down timeout */ 3084 uint16_t max_loop_id; 3085 uint16_t max_fibre_devices; /* Maximum number of targets */ 3086 3087 uint16_t fb_rev; 3088 uint16_t min_external_loopid; /* First external loop Id */ 3089 3090 #define PORT_SPEED_UNKNOWN 0xFFFF 3091 #define PORT_SPEED_1GB 0x00 3092 #define PORT_SPEED_2GB 0x01 3093 #define PORT_SPEED_4GB 0x03 3094 #define PORT_SPEED_8GB 0x04 3095 #define PORT_SPEED_16GB 0x05 3096 #define PORT_SPEED_32GB 0x06 3097 #define PORT_SPEED_10GB 0x13 3098 uint16_t link_data_rate; /* F/W operating speed */ 3099 3100 uint8_t current_topology; 3101 uint8_t prev_topology; 3102 #define ISP_CFG_NL 1 3103 #define ISP_CFG_N 2 3104 #define ISP_CFG_FL 4 3105 #define ISP_CFG_F 8 3106 3107 uint8_t operating_mode; /* F/W operating mode */ 3108 #define LOOP 0 3109 #define P2P 1 3110 #define LOOP_P2P 2 3111 #define P2P_LOOP 3 3112 uint8_t interrupts_on; 3113 uint32_t isp_abort_cnt; 3114 3115 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532 3116 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432 3117 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001 3118 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031 3119 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031 3120 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071 3121 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271 3122 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261 3123 3124 uint32_t isp_type; 3125 #define DT_ISP2100 BIT_0 3126 #define DT_ISP2200 BIT_1 3127 #define DT_ISP2300 BIT_2 3128 #define DT_ISP2312 BIT_3 3129 #define DT_ISP2322 BIT_4 3130 #define DT_ISP6312 BIT_5 3131 #define DT_ISP6322 BIT_6 3132 #define DT_ISP2422 BIT_7 3133 #define DT_ISP2432 BIT_8 3134 #define DT_ISP5422 BIT_9 3135 #define DT_ISP5432 BIT_10 3136 #define DT_ISP2532 BIT_11 3137 #define DT_ISP8432 BIT_12 3138 #define DT_ISP8001 BIT_13 3139 #define DT_ISP8021 BIT_14 3140 #define DT_ISP2031 BIT_15 3141 #define DT_ISP8031 BIT_16 3142 #define DT_ISPFX00 BIT_17 3143 #define DT_ISP8044 BIT_18 3144 #define DT_ISP2071 BIT_19 3145 #define DT_ISP2271 BIT_20 3146 #define DT_ISP2261 BIT_21 3147 #define DT_ISP_LAST (DT_ISP2261 << 1) 3148 3149 uint32_t device_type; 3150 #define DT_T10_PI BIT_25 3151 #define DT_IIDMA BIT_26 3152 #define DT_FWI2 BIT_27 3153 #define DT_ZIO_SUPPORTED BIT_28 3154 #define DT_OEM_001 BIT_29 3155 #define DT_ISP2200A BIT_30 3156 #define DT_EXTENDED_IDS BIT_31 3157 3158 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1)) 3159 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100) 3160 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200) 3161 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300) 3162 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312) 3163 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322) 3164 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312) 3165 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322) 3166 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422) 3167 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432) 3168 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422) 3169 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432) 3170 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) 3171 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) 3172 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) 3173 #define IS_QLA81XX(ha) (IS_QLA8001(ha)) 3174 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) 3175 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044) 3176 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031) 3177 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031) 3178 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00) 3179 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071) 3180 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271) 3181 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261) 3182 3183 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ 3184 IS_QLA6312(ha) || IS_QLA6322(ha)) 3185 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha)) 3186 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha)) 3187 #define IS_QLA25XX(ha) (IS_QLA2532(ha)) 3188 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha)) 3189 #define IS_QLA84XX(ha) (IS_QLA8432(ha)) 3190 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha)) 3191 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ 3192 IS_QLA84XX(ha)) 3193 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \ 3194 IS_QLA8031(ha) || IS_QLA8044(ha)) 3195 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha)) 3196 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ 3197 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ 3198 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \ 3199 IS_QLA8044(ha) || IS_QLA27XX(ha)) 3200 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3201 IS_QLA27XX(ha)) 3202 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled) 3203 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3204 IS_QLA27XX(ha)) 3205 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \ 3206 IS_QLA27XX(ha)) 3207 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha)) 3208 3209 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI) 3210 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA) 3211 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2) 3212 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED) 3213 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001) 3214 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS) 3215 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED) 3216 #define IS_MQUE_CAPABLE(ha) ((ha)->mqenable || IS_QLA83XX(ha) || \ 3217 IS_QLA27XX(ha)) 3218 #define IS_BIDI_CAPABLE(ha) ((IS_QLA25XX(ha) || IS_QLA2031(ha))) 3219 /* Bit 21 of fw_attributes decides the MCTP capabilities */ 3220 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \ 3221 ((ha)->fw_attributes_ext[0] & BIT_0)) 3222 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3223 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3224 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0) 3225 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3226 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \ 3227 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22)) 3228 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3229 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length) 3230 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha)) 3231 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3232 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha)) 3233 3234 /* HBA serial number */ 3235 uint8_t serial0; 3236 uint8_t serial1; 3237 uint8_t serial2; 3238 3239 /* NVRAM configuration data */ 3240 #define MAX_NVRAM_SIZE 4096 3241 #define VPD_OFFSET MAX_NVRAM_SIZE / 2 3242 uint16_t nvram_size; 3243 uint16_t nvram_base; 3244 void *nvram; 3245 uint16_t vpd_size; 3246 uint16_t vpd_base; 3247 void *vpd; 3248 3249 uint16_t loop_reset_delay; 3250 uint8_t retry_count; 3251 uint8_t login_timeout; 3252 uint16_t r_a_tov; 3253 int port_down_retry_count; 3254 uint8_t mbx_count; 3255 uint8_t aen_mbx_count; 3256 3257 uint32_t login_retry_count; 3258 /* SNS command interfaces. */ 3259 ms_iocb_entry_t *ms_iocb; 3260 dma_addr_t ms_iocb_dma; 3261 struct ct_sns_pkt *ct_sns; 3262 dma_addr_t ct_sns_dma; 3263 /* SNS command interfaces for 2200. */ 3264 struct sns_cmd_pkt *sns_cmd; 3265 dma_addr_t sns_cmd_dma; 3266 3267 #define SFP_DEV_SIZE 256 3268 #define SFP_BLOCK_SIZE 64 3269 void *sfp_data; 3270 dma_addr_t sfp_data_dma; 3271 3272 #define XGMAC_DATA_SIZE 4096 3273 void *xgmac_data; 3274 dma_addr_t xgmac_data_dma; 3275 3276 #define DCBX_TLV_DATA_SIZE 4096 3277 void *dcbx_tlv; 3278 dma_addr_t dcbx_tlv_dma; 3279 3280 struct task_struct *dpc_thread; 3281 uint8_t dpc_active; /* DPC routine is active */ 3282 3283 dma_addr_t gid_list_dma; 3284 struct gid_list_info *gid_list; 3285 int gid_list_info_size; 3286 3287 /* Small DMA pool allocations -- maximum 256 bytes in length. */ 3288 #define DMA_POOL_SIZE 256 3289 struct dma_pool *s_dma_pool; 3290 3291 dma_addr_t init_cb_dma; 3292 init_cb_t *init_cb; 3293 int init_cb_size; 3294 dma_addr_t ex_init_cb_dma; 3295 struct ex_init_cb_81xx *ex_init_cb; 3296 3297 void *async_pd; 3298 dma_addr_t async_pd_dma; 3299 3300 #define ENABLE_EXTENDED_LOGIN BIT_7 3301 3302 /* Extended Logins */ 3303 void *exlogin_buf; 3304 dma_addr_t exlogin_buf_dma; 3305 int exlogin_size; 3306 3307 #define ENABLE_EXCHANGE_OFFLD BIT_2 3308 3309 /* Exchange Offload */ 3310 void *exchoffld_buf; 3311 dma_addr_t exchoffld_buf_dma; 3312 int exchoffld_size; 3313 int exchoffld_count; 3314 3315 void *swl; 3316 3317 /* These are used by mailbox operations. */ 3318 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; 3319 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT]; 3320 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00]; 3321 3322 mbx_cmd_t *mcp; 3323 struct mbx_cmd_32 *mcp32; 3324 3325 unsigned long mbx_cmd_flags; 3326 #define MBX_INTERRUPT 1 3327 #define MBX_INTR_WAIT 2 3328 #define MBX_UPDATE_FLASH_ACTIVE 3 3329 3330 struct mutex vport_lock; /* Virtual port synchronization */ 3331 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */ 3332 struct completion mbx_cmd_comp; /* Serialize mbx access */ 3333 struct completion mbx_intr_comp; /* Used for completion notification */ 3334 struct completion dcbx_comp; /* For set port config notification */ 3335 struct completion lb_portup_comp; /* Used to wait for link up during 3336 * loopback */ 3337 #define DCBX_COMP_TIMEOUT 20 3338 #define LB_PORTUP_COMP_TIMEOUT 10 3339 3340 int notify_dcbx_comp; 3341 int notify_lb_portup_comp; 3342 struct mutex selflogin_lock; 3343 3344 /* Basic firmware related information. */ 3345 uint16_t fw_major_version; 3346 uint16_t fw_minor_version; 3347 uint16_t fw_subminor_version; 3348 uint16_t fw_attributes; 3349 uint16_t fw_attributes_h; 3350 uint16_t fw_attributes_ext[2]; 3351 uint32_t fw_memory_size; 3352 uint32_t fw_transfer_size; 3353 uint32_t fw_srisc_address; 3354 #define RISC_START_ADDRESS_2100 0x1000 3355 #define RISC_START_ADDRESS_2300 0x800 3356 #define RISC_START_ADDRESS_2400 0x100000 3357 3358 uint16_t orig_fw_tgt_xcb_count; 3359 uint16_t cur_fw_tgt_xcb_count; 3360 uint16_t orig_fw_xcb_count; 3361 uint16_t cur_fw_xcb_count; 3362 uint16_t orig_fw_iocb_count; 3363 uint16_t cur_fw_iocb_count; 3364 uint16_t fw_max_fcf_count; 3365 3366 uint32_t fw_shared_ram_start; 3367 uint32_t fw_shared_ram_end; 3368 uint32_t fw_ddr_ram_start; 3369 uint32_t fw_ddr_ram_end; 3370 3371 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */ 3372 uint8_t fw_seriallink_options[4]; 3373 uint16_t fw_seriallink_options24[4]; 3374 3375 uint8_t mpi_version[3]; 3376 uint32_t mpi_capabilities; 3377 uint8_t phy_version[3]; 3378 uint8_t pep_version[3]; 3379 3380 /* Firmware dump template */ 3381 void *fw_dump_template; 3382 uint32_t fw_dump_template_len; 3383 /* Firmware dump information. */ 3384 struct qla2xxx_fw_dump *fw_dump; 3385 uint32_t fw_dump_len; 3386 int fw_dumped; 3387 unsigned long fw_dump_cap_flags; 3388 #define RISC_PAUSE_CMPL 0 3389 #define DMA_SHUTDOWN_CMPL 1 3390 #define ISP_RESET_CMPL 2 3391 #define RISC_RDY_AFT_RESET 3 3392 #define RISC_SRAM_DUMP_CMPL 4 3393 #define RISC_EXT_MEM_DUMP_CMPL 5 3394 #define ISP_MBX_RDY 6 3395 #define ISP_SOFT_RESET_CMPL 7 3396 int fw_dump_reading; 3397 int prev_minidump_failed; 3398 dma_addr_t eft_dma; 3399 void *eft; 3400 /* Current size of mctp dump is 0x086064 bytes */ 3401 #define MCTP_DUMP_SIZE 0x086064 3402 dma_addr_t mctp_dump_dma; 3403 void *mctp_dump; 3404 int mctp_dumped; 3405 int mctp_dump_reading; 3406 uint32_t chain_offset; 3407 struct dentry *dfs_dir; 3408 struct dentry *dfs_fce; 3409 struct dentry *dfs_tgt_counters; 3410 struct dentry *dfs_fw_resource_cnt; 3411 3412 dma_addr_t fce_dma; 3413 void *fce; 3414 uint32_t fce_bufs; 3415 uint16_t fce_mb[8]; 3416 uint64_t fce_wr, fce_rd; 3417 struct mutex fce_mutex; 3418 3419 uint32_t pci_attr; 3420 uint16_t chip_revision; 3421 3422 uint16_t product_id[4]; 3423 3424 uint8_t model_number[16+1]; 3425 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" 3426 char model_desc[80]; 3427 uint8_t adapter_id[16+1]; 3428 3429 /* Option ROM information. */ 3430 char *optrom_buffer; 3431 uint32_t optrom_size; 3432 int optrom_state; 3433 #define QLA_SWAITING 0 3434 #define QLA_SREADING 1 3435 #define QLA_SWRITING 2 3436 uint32_t optrom_region_start; 3437 uint32_t optrom_region_size; 3438 struct mutex optrom_mutex; 3439 3440 /* PCI expansion ROM image information. */ 3441 #define ROM_CODE_TYPE_BIOS 0 3442 #define ROM_CODE_TYPE_FCODE 1 3443 #define ROM_CODE_TYPE_EFI 3 3444 uint8_t bios_revision[2]; 3445 uint8_t efi_revision[2]; 3446 uint8_t fcode_revision[16]; 3447 uint32_t fw_revision[4]; 3448 3449 uint32_t gold_fw_version[4]; 3450 3451 /* Offsets for flash/nvram access (set to ~0 if not used). */ 3452 uint32_t flash_conf_off; 3453 uint32_t flash_data_off; 3454 uint32_t nvram_conf_off; 3455 uint32_t nvram_data_off; 3456 3457 uint32_t fdt_wrt_disable; 3458 uint32_t fdt_wrt_enable; 3459 uint32_t fdt_erase_cmd; 3460 uint32_t fdt_block_size; 3461 uint32_t fdt_unprotect_sec_cmd; 3462 uint32_t fdt_protect_sec_cmd; 3463 uint32_t fdt_wrt_sts_reg_cmd; 3464 3465 uint32_t flt_region_flt; 3466 uint32_t flt_region_fdt; 3467 uint32_t flt_region_boot; 3468 uint32_t flt_region_boot_sec; 3469 uint32_t flt_region_fw; 3470 uint32_t flt_region_fw_sec; 3471 uint32_t flt_region_vpd_nvram; 3472 uint32_t flt_region_vpd; 3473 uint32_t flt_region_vpd_sec; 3474 uint32_t flt_region_nvram; 3475 uint32_t flt_region_npiv_conf; 3476 uint32_t flt_region_gold_fw; 3477 uint32_t flt_region_fcp_prio; 3478 uint32_t flt_region_bootload; 3479 uint32_t flt_region_img_status_pri; 3480 uint32_t flt_region_img_status_sec; 3481 uint8_t active_image; 3482 3483 /* Needed for BEACON */ 3484 uint16_t beacon_blink_led; 3485 uint8_t beacon_color_state; 3486 #define QLA_LED_GRN_ON 0x01 3487 #define QLA_LED_YLW_ON 0x02 3488 #define QLA_LED_ABR_ON 0x04 3489 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */ 3490 /* ISP2322: red, green, amber. */ 3491 uint16_t zio_mode; 3492 uint16_t zio_timer; 3493 3494 struct qla_msix_entry *msix_entries; 3495 3496 struct list_head vp_list; /* list of VP */ 3497 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) / 3498 sizeof(unsigned long)]; 3499 uint16_t num_vhosts; /* number of vports created */ 3500 uint16_t num_vsans; /* number of vsan created */ 3501 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */ 3502 int cur_vport_count; 3503 3504 struct qla_chip_state_84xx *cs84xx; 3505 struct isp_operations *isp_ops; 3506 struct workqueue_struct *wq; 3507 struct qlfc_fw fw_buf; 3508 3509 /* FCP_CMND priority support */ 3510 struct qla_fcp_prio_cfg *fcp_prio_cfg; 3511 3512 struct dma_pool *dl_dma_pool; 3513 #define DSD_LIST_DMA_POOL_SIZE 512 3514 3515 struct dma_pool *fcp_cmnd_dma_pool; 3516 mempool_t *ctx_mempool; 3517 #define FCP_CMND_DMA_POOL_SIZE 512 3518 3519 void __iomem *nx_pcibase; /* Base I/O address */ 3520 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */ 3521 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */ 3522 3523 uint32_t crb_win; 3524 uint32_t curr_window; 3525 uint32_t ddr_mn_window; 3526 unsigned long mn_win_crb; 3527 unsigned long ms_win_crb; 3528 int qdr_sn_window; 3529 uint32_t fcoe_dev_init_timeout; 3530 uint32_t fcoe_reset_timeout; 3531 rwlock_t hw_lock; 3532 uint16_t portnum; /* port number */ 3533 int link_width; 3534 struct fw_blob *hablob; 3535 struct qla82xx_legacy_intr_set nx_legacy_intr; 3536 3537 uint16_t gbl_dsd_inuse; 3538 uint16_t gbl_dsd_avail; 3539 struct list_head gbl_dsd_list; 3540 #define NUM_DSD_CHAIN 4096 3541 3542 uint8_t fw_type; 3543 __le32 file_prd_off; /* File firmware product offset */ 3544 3545 uint32_t md_template_size; 3546 void *md_tmplt_hdr; 3547 dma_addr_t md_tmplt_hdr_dma; 3548 void *md_dump; 3549 uint32_t md_dump_size; 3550 3551 void *loop_id_map; 3552 3553 /* QLA83XX IDC specific fields */ 3554 uint32_t idc_audit_ts; 3555 uint32_t idc_extend_tmo; 3556 3557 /* DPC low-priority workqueue */ 3558 struct workqueue_struct *dpc_lp_wq; 3559 struct work_struct idc_aen; 3560 /* DPC high-priority workqueue */ 3561 struct workqueue_struct *dpc_hp_wq; 3562 struct work_struct nic_core_reset; 3563 struct work_struct idc_state_handler; 3564 struct work_struct nic_core_unrecoverable; 3565 struct work_struct board_disable; 3566 3567 struct mr_data_fx00 mr; 3568 uint32_t chip_reset; 3569 3570 struct qlt_hw_data tgt; 3571 int allow_cna_fw_dump; 3572 }; 3573 3574 struct qla_tgt_counters { 3575 uint64_t qla_core_sbt_cmd; 3576 uint64_t core_qla_que_buf; 3577 uint64_t qla_core_ret_ctio; 3578 uint64_t core_qla_snd_status; 3579 uint64_t qla_core_ret_sta_ctio; 3580 uint64_t core_qla_free_cmd; 3581 uint64_t num_q_full_sent; 3582 uint64_t num_alloc_iocb_failed; 3583 uint64_t num_term_xchg_sent; 3584 }; 3585 3586 /* 3587 * Qlogic scsi host structure 3588 */ 3589 typedef struct scsi_qla_host { 3590 struct list_head list; 3591 struct list_head vp_fcports; /* list of fcports */ 3592 struct list_head work_list; 3593 spinlock_t work_lock; 3594 3595 /* Commonly used flags and state information. */ 3596 struct Scsi_Host *host; 3597 unsigned long host_no; 3598 uint8_t host_str[16]; 3599 3600 volatile struct { 3601 uint32_t init_done :1; 3602 uint32_t online :1; 3603 uint32_t reset_active :1; 3604 3605 uint32_t management_server_logged_in :1; 3606 uint32_t process_response_queue :1; 3607 uint32_t difdix_supported:1; 3608 uint32_t delete_progress:1; 3609 3610 uint32_t fw_tgt_reported:1; 3611 uint32_t bbcr_enable:1; 3612 } flags; 3613 3614 atomic_t loop_state; 3615 #define LOOP_TIMEOUT 1 3616 #define LOOP_DOWN 2 3617 #define LOOP_UP 3 3618 #define LOOP_UPDATE 4 3619 #define LOOP_READY 5 3620 #define LOOP_DEAD 6 3621 3622 unsigned long dpc_flags; 3623 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */ 3624 #define RESET_ACTIVE 1 3625 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */ 3626 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */ 3627 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */ 3628 #define LOOP_RESYNC_ACTIVE 5 3629 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */ 3630 #define RSCN_UPDATE 7 /* Perform an RSCN update. */ 3631 #define RELOGIN_NEEDED 8 3632 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */ 3633 #define ISP_ABORT_RETRY 10 /* ISP aborted. */ 3634 #define BEACON_BLINK_NEEDED 11 3635 #define REGISTER_FDMI_NEEDED 12 3636 #define FCPORT_UPDATE_NEEDED 13 3637 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ 3638 #define UNLOADING 15 3639 #define NPIV_CONFIG_NEEDED 16 3640 #define ISP_UNRECOVERABLE 17 3641 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ 3642 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */ 3643 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */ 3644 #define SCR_PENDING 21 /* SCR in target mode */ 3645 #define PORT_UPDATE_NEEDED 22 3646 #define FX00_RESET_RECOVERY 23 3647 #define FX00_TARGET_SCAN 24 3648 #define FX00_CRITEMP_RECOVERY 25 3649 #define FX00_HOST_INFO_RESEND 26 3650 3651 unsigned long pci_flags; 3652 #define PFLG_DISCONNECTED 0 /* PCI device removed */ 3653 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */ 3654 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */ 3655 #define PCI_ERR 30 3656 3657 uint32_t device_flags; 3658 #define SWITCH_FOUND BIT_0 3659 #define DFLG_NO_CABLE BIT_1 3660 #define DFLG_DEV_FAILED BIT_5 3661 3662 /* ISP configuration data. */ 3663 uint16_t loop_id; /* Host adapter loop id */ 3664 uint16_t self_login_loop_id; /* host adapter loop id 3665 * get it on self login 3666 */ 3667 fc_port_t bidir_fcport; /* fcport used for bidir cmnds 3668 * no need of allocating it for 3669 * each command 3670 */ 3671 3672 port_id_t d_id; /* Host adapter port id */ 3673 uint8_t marker_needed; 3674 uint16_t mgmt_svr_loop_id; 3675 3676 3677 3678 /* Timeout timers. */ 3679 uint8_t loop_down_abort_time; /* port down timer */ 3680 atomic_t loop_down_timer; /* loop down timer */ 3681 uint8_t link_down_timeout; /* link down timeout */ 3682 3683 uint32_t timer_active; 3684 struct timer_list timer; 3685 3686 uint8_t node_name[WWN_SIZE]; 3687 uint8_t port_name[WWN_SIZE]; 3688 uint8_t fabric_node_name[WWN_SIZE]; 3689 3690 uint16_t fcoe_vlan_id; 3691 uint16_t fcoe_fcf_idx; 3692 uint8_t fcoe_vn_port_mac[6]; 3693 3694 /* list of commands waiting on workqueue */ 3695 struct list_head qla_cmd_list; 3696 struct list_head qla_sess_op_cmd_list; 3697 spinlock_t cmd_list_lock; 3698 3699 /* Counter to detect races between ELS and RSCN events */ 3700 atomic_t generation_tick; 3701 /* Time when global fcport update has been scheduled */ 3702 int total_fcport_update_gen; 3703 /* List of pending LOGOs, protected by tgt_mutex */ 3704 struct list_head logo_list; 3705 /* List of pending PLOGI acks, protected by hw lock */ 3706 struct list_head plogi_ack_list; 3707 3708 uint32_t vp_abort_cnt; 3709 3710 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */ 3711 uint16_t vp_idx; /* vport ID */ 3712 3713 unsigned long vp_flags; 3714 #define VP_IDX_ACQUIRED 0 /* bit no 0 */ 3715 #define VP_CREATE_NEEDED 1 3716 #define VP_BIND_NEEDED 2 3717 #define VP_DELETE_NEEDED 3 3718 #define VP_SCR_NEEDED 4 /* State Change Request registration */ 3719 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */ 3720 atomic_t vp_state; 3721 #define VP_OFFLINE 0 3722 #define VP_ACTIVE 1 3723 #define VP_FAILED 2 3724 // #define VP_DISABLE 3 3725 uint16_t vp_err_state; 3726 uint16_t vp_prev_err_state; 3727 #define VP_ERR_UNKWN 0 3728 #define VP_ERR_PORTDWN 1 3729 #define VP_ERR_FAB_UNSUPPORTED 2 3730 #define VP_ERR_FAB_NORESOURCES 3 3731 #define VP_ERR_FAB_LOGOUT 4 3732 #define VP_ERR_ADAP_NORESOURCES 5 3733 struct qla_hw_data *hw; 3734 struct scsi_qlt_host vha_tgt; 3735 struct req_que *req; 3736 int fw_heartbeat_counter; 3737 int seconds_since_last_heartbeat; 3738 struct fc_host_statistics fc_host_stat; 3739 struct qla_statistics qla_stats; 3740 struct bidi_statistics bidi_stats; 3741 3742 atomic_t vref_count; 3743 struct qla8044_reset_template reset_tmplt; 3744 struct qla_tgt_counters tgt_counters; 3745 uint16_t bbcr; 3746 wait_queue_head_t vref_waitq; 3747 } scsi_qla_host_t; 3748 3749 struct qla27xx_image_status { 3750 uint8_t image_status_mask; 3751 uint16_t generation_number; 3752 uint8_t reserved[3]; 3753 uint8_t ver_minor; 3754 uint8_t ver_major; 3755 uint32_t checksum; 3756 uint32_t signature; 3757 } __packed; 3758 3759 #define SET_VP_IDX 1 3760 #define SET_AL_PA 2 3761 #define RESET_VP_IDX 3 3762 #define RESET_AL_PA 4 3763 struct qla_tgt_vp_map { 3764 uint8_t idx; 3765 scsi_qla_host_t *vha; 3766 }; 3767 3768 /* 3769 * Macros to help code, maintain, etc. 3770 */ 3771 #define LOOP_TRANSITION(ha) \ 3772 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 3773 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \ 3774 atomic_read(&ha->loop_state) == LOOP_DOWN) 3775 3776 #define STATE_TRANSITION(ha) \ 3777 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \ 3778 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags)) 3779 3780 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \ 3781 atomic_inc(&__vha->vref_count); \ 3782 mb(); \ 3783 if (__vha->flags.delete_progress) { \ 3784 atomic_dec(&__vha->vref_count); \ 3785 wake_up(&__vha->vref_waitq); \ 3786 __bail = 1; \ 3787 } else { \ 3788 __bail = 0; \ 3789 } \ 3790 } while (0) 3791 3792 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \ 3793 atomic_dec(&__vha->vref_count); \ 3794 wake_up(&__vha->vref_waitq); \ 3795 } while (0) 3796 3797 /* 3798 * qla2x00 local function return status codes 3799 */ 3800 #define MBS_MASK 0x3fff 3801 3802 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK) 3803 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK) 3804 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK) 3805 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK) 3806 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK) 3807 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK) 3808 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK) 3809 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK) 3810 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK) 3811 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK) 3812 3813 #define QLA_FUNCTION_TIMEOUT 0x100 3814 #define QLA_FUNCTION_PARAMETER_ERROR 0x101 3815 #define QLA_FUNCTION_FAILED 0x102 3816 #define QLA_MEMORY_ALLOC_FAILED 0x103 3817 #define QLA_LOCK_TIMEOUT 0x104 3818 #define QLA_ABORTED 0x105 3819 #define QLA_SUSPENDED 0x106 3820 #define QLA_BUSY 0x107 3821 #define QLA_ALREADY_REGISTERED 0x109 3822 3823 #define NVRAM_DELAY() udelay(10) 3824 3825 /* 3826 * Flash support definitions 3827 */ 3828 #define OPTROM_SIZE_2300 0x20000 3829 #define OPTROM_SIZE_2322 0x100000 3830 #define OPTROM_SIZE_24XX 0x100000 3831 #define OPTROM_SIZE_25XX 0x200000 3832 #define OPTROM_SIZE_81XX 0x400000 3833 #define OPTROM_SIZE_82XX 0x800000 3834 #define OPTROM_SIZE_83XX 0x1000000 3835 3836 #define OPTROM_BURST_SIZE 0x1000 3837 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) 3838 3839 #define QLA_DSDS_PER_IOCB 37 3840 3841 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr) 3842 3843 #define QLA_SG_ALL 1024 3844 3845 enum nexus_wait_type { 3846 WAIT_HOST = 0, 3847 WAIT_TARGET, 3848 WAIT_LUN, 3849 }; 3850 3851 #include "qla_gbl.h" 3852 #include "qla_dbg.h" 3853 #include "qla_inline.h" 3854 #endif 3855