Home
last modified time | relevance | path

Searched refs:DUMPREG (Results 1 – 17 of 17) sorted by relevance

/drivers/media/platform/ti-vpe/
Dsc.c27 #define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, \ in sc_dump_regs() macro
30 DUMPREG(SC0); in sc_dump_regs()
31 DUMPREG(SC1); in sc_dump_regs()
32 DUMPREG(SC2); in sc_dump_regs()
33 DUMPREG(SC3); in sc_dump_regs()
34 DUMPREG(SC4); in sc_dump_regs()
35 DUMPREG(SC5); in sc_dump_regs()
36 DUMPREG(SC6); in sc_dump_regs()
37 DUMPREG(SC8); in sc_dump_regs()
38 DUMPREG(SC9); in sc_dump_regs()
[all …]
Dvpdma.c273 #define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, read_reg(vpdma, VPDMA_##r)) in vpdma_dump_regs() macro
277 DUMPREG(PID); in vpdma_dump_regs()
278 DUMPREG(LIST_ADDR); in vpdma_dump_regs()
279 DUMPREG(LIST_ATTR); in vpdma_dump_regs()
280 DUMPREG(LIST_STAT_SYNC); in vpdma_dump_regs()
281 DUMPREG(BG_RGB); in vpdma_dump_regs()
282 DUMPREG(BG_YUV); in vpdma_dump_regs()
283 DUMPREG(SETUP); in vpdma_dump_regs()
284 DUMPREG(MAX_SIZE1); in vpdma_dump_regs()
285 DUMPREG(MAX_SIZE2); in vpdma_dump_regs()
[all …]
Dcsc.c96 #define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, \ in csc_dump_regs() macro
99 DUMPREG(CSC00); in csc_dump_regs()
100 DUMPREG(CSC01); in csc_dump_regs()
101 DUMPREG(CSC02); in csc_dump_regs()
102 DUMPREG(CSC03); in csc_dump_regs()
103 DUMPREG(CSC04); in csc_dump_regs()
104 DUMPREG(CSC05); in csc_dump_regs()
106 #undef DUMPREG in csc_dump_regs()
Dvpe.c925 #define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r)) in vpe_dump_regs() macro
929 DUMPREG(PID); in vpe_dump_regs()
930 DUMPREG(SYSCONFIG); in vpe_dump_regs()
931 DUMPREG(INT0_STATUS0_RAW); in vpe_dump_regs()
932 DUMPREG(INT0_STATUS0); in vpe_dump_regs()
933 DUMPREG(INT0_ENABLE0); in vpe_dump_regs()
934 DUMPREG(INT0_STATUS1_RAW); in vpe_dump_regs()
935 DUMPREG(INT0_STATUS1); in vpe_dump_regs()
936 DUMPREG(INT0_ENABLE1); in vpe_dump_regs()
937 DUMPREG(CLK_ENABLE); in vpe_dump_regs()
[all …]
/drivers/video/fbdev/omap2/omapfb/dss/
Dvenc.c659 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r)) in venc_dump_regs() macro
664 DUMPREG(VENC_F_CONTROL); in venc_dump_regs()
665 DUMPREG(VENC_VIDOUT_CTRL); in venc_dump_regs()
666 DUMPREG(VENC_SYNC_CTRL); in venc_dump_regs()
667 DUMPREG(VENC_LLEN); in venc_dump_regs()
668 DUMPREG(VENC_FLENS); in venc_dump_regs()
669 DUMPREG(VENC_HFLTR_CTRL); in venc_dump_regs()
670 DUMPREG(VENC_CC_CARR_WSS_CARR); in venc_dump_regs()
671 DUMPREG(VENC_C_PHASE); in venc_dump_regs()
672 DUMPREG(VENC_GAIN_U); in venc_dump_regs()
[all …]
Dhdmi_wp.c24 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump() macro
26 DUMPREG(HDMI_WP_REVISION); in hdmi_wp_dump()
27 DUMPREG(HDMI_WP_SYSCONFIG); in hdmi_wp_dump()
28 DUMPREG(HDMI_WP_IRQSTATUS_RAW); in hdmi_wp_dump()
29 DUMPREG(HDMI_WP_IRQSTATUS); in hdmi_wp_dump()
30 DUMPREG(HDMI_WP_IRQENABLE_SET); in hdmi_wp_dump()
31 DUMPREG(HDMI_WP_IRQENABLE_CLR); in hdmi_wp_dump()
32 DUMPREG(HDMI_WP_IRQWAKEEN); in hdmi_wp_dump()
33 DUMPREG(HDMI_WP_PWR_CTRL); in hdmi_wp_dump()
34 DUMPREG(HDMI_WP_DEBOUNCE); in hdmi_wp_dump()
[all …]
Drfbi.c802 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r)) in rfbi_dump_regs() macro
807 DUMPREG(RFBI_REVISION); in rfbi_dump_regs()
808 DUMPREG(RFBI_SYSCONFIG); in rfbi_dump_regs()
809 DUMPREG(RFBI_SYSSTATUS); in rfbi_dump_regs()
810 DUMPREG(RFBI_CONTROL); in rfbi_dump_regs()
811 DUMPREG(RFBI_PIXEL_CNT); in rfbi_dump_regs()
812 DUMPREG(RFBI_LINE_NUMBER); in rfbi_dump_regs()
813 DUMPREG(RFBI_CMD); in rfbi_dump_regs()
814 DUMPREG(RFBI_PARAM); in rfbi_dump_regs()
815 DUMPREG(RFBI_DATA); in rfbi_dump_regs()
[all …]
Ddispc.c3520 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) in dispc_dump_regs() macro
3526 DUMPREG(DISPC_REVISION); in dispc_dump_regs()
3527 DUMPREG(DISPC_SYSCONFIG); in dispc_dump_regs()
3528 DUMPREG(DISPC_SYSSTATUS); in dispc_dump_regs()
3529 DUMPREG(DISPC_IRQSTATUS); in dispc_dump_regs()
3530 DUMPREG(DISPC_IRQENABLE); in dispc_dump_regs()
3531 DUMPREG(DISPC_CONTROL); in dispc_dump_regs()
3532 DUMPREG(DISPC_CONFIG); in dispc_dump_regs()
3533 DUMPREG(DISPC_CAPABLE); in dispc_dump_regs()
3534 DUMPREG(DISPC_LINE_STATUS); in dispc_dump_regs()
[all …]
Ddsi.c1652 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) in dsi_dump_dsidev_regs() macro
1658 DUMPREG(DSI_REVISION); in dsi_dump_dsidev_regs()
1659 DUMPREG(DSI_SYSCONFIG); in dsi_dump_dsidev_regs()
1660 DUMPREG(DSI_SYSSTATUS); in dsi_dump_dsidev_regs()
1661 DUMPREG(DSI_IRQSTATUS); in dsi_dump_dsidev_regs()
1662 DUMPREG(DSI_IRQENABLE); in dsi_dump_dsidev_regs()
1663 DUMPREG(DSI_CTRL); in dsi_dump_dsidev_regs()
1664 DUMPREG(DSI_COMPLEXIO_CFG1); in dsi_dump_dsidev_regs()
1665 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); in dsi_dump_dsidev_regs()
1666 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); in dsi_dump_dsidev_regs()
[all …]
Ddss.c384 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) in dss_dump_regs() macro
389 DUMPREG(DSS_REVISION); in dss_dump_regs()
390 DUMPREG(DSS_SYSCONFIG); in dss_dump_regs()
391 DUMPREG(DSS_SYSSTATUS); in dss_dump_regs()
392 DUMPREG(DSS_CONTROL); in dss_dump_regs()
396 DUMPREG(DSS_SDI_CONTROL); in dss_dump_regs()
397 DUMPREG(DSS_PLL_CONTROL); in dss_dump_regs()
398 DUMPREG(DSS_SDI_STATUS); in dss_dump_regs()
402 #undef DUMPREG in dss_dump_regs()
/drivers/gpu/drm/omapdrm/dss/
Dvenc.c670 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r)) in venc_dump_regs() macro
675 DUMPREG(VENC_F_CONTROL); in venc_dump_regs()
676 DUMPREG(VENC_VIDOUT_CTRL); in venc_dump_regs()
677 DUMPREG(VENC_SYNC_CTRL); in venc_dump_regs()
678 DUMPREG(VENC_LLEN); in venc_dump_regs()
679 DUMPREG(VENC_FLENS); in venc_dump_regs()
680 DUMPREG(VENC_HFLTR_CTRL); in venc_dump_regs()
681 DUMPREG(VENC_CC_CARR_WSS_CARR); in venc_dump_regs()
682 DUMPREG(VENC_C_PHASE); in venc_dump_regs()
683 DUMPREG(VENC_GAIN_U); in venc_dump_regs()
[all …]
Dhdmi_wp.c25 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump() macro
27 DUMPREG(HDMI_WP_REVISION); in hdmi_wp_dump()
28 DUMPREG(HDMI_WP_SYSCONFIG); in hdmi_wp_dump()
29 DUMPREG(HDMI_WP_IRQSTATUS_RAW); in hdmi_wp_dump()
30 DUMPREG(HDMI_WP_IRQSTATUS); in hdmi_wp_dump()
31 DUMPREG(HDMI_WP_IRQENABLE_SET); in hdmi_wp_dump()
32 DUMPREG(HDMI_WP_IRQENABLE_CLR); in hdmi_wp_dump()
33 DUMPREG(HDMI_WP_IRQWAKEEN); in hdmi_wp_dump()
34 DUMPREG(HDMI_WP_PWR_CTRL); in hdmi_wp_dump()
35 DUMPREG(HDMI_WP_DEBOUNCE); in hdmi_wp_dump()
[all …]
Drfbi.c802 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, rfbi_read_reg(r)) in rfbi_dump_regs() macro
807 DUMPREG(RFBI_REVISION); in rfbi_dump_regs()
808 DUMPREG(RFBI_SYSCONFIG); in rfbi_dump_regs()
809 DUMPREG(RFBI_SYSSTATUS); in rfbi_dump_regs()
810 DUMPREG(RFBI_CONTROL); in rfbi_dump_regs()
811 DUMPREG(RFBI_PIXEL_CNT); in rfbi_dump_regs()
812 DUMPREG(RFBI_LINE_NUMBER); in rfbi_dump_regs()
813 DUMPREG(RFBI_CMD); in rfbi_dump_regs()
814 DUMPREG(RFBI_PARAM); in rfbi_dump_regs()
815 DUMPREG(RFBI_DATA); in rfbi_dump_regs()
[all …]
Ddispc.c3502 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) in dispc_dump_regs() macro
3508 DUMPREG(DISPC_REVISION); in dispc_dump_regs()
3509 DUMPREG(DISPC_SYSCONFIG); in dispc_dump_regs()
3510 DUMPREG(DISPC_SYSSTATUS); in dispc_dump_regs()
3511 DUMPREG(DISPC_IRQSTATUS); in dispc_dump_regs()
3512 DUMPREG(DISPC_IRQENABLE); in dispc_dump_regs()
3513 DUMPREG(DISPC_CONTROL); in dispc_dump_regs()
3514 DUMPREG(DISPC_CONFIG); in dispc_dump_regs()
3515 DUMPREG(DISPC_CAPABLE); in dispc_dump_regs()
3516 DUMPREG(DISPC_LINE_STATUS); in dispc_dump_regs()
[all …]
Ddsi.c1651 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) in dsi_dump_dsidev_regs() macro
1657 DUMPREG(DSI_REVISION); in dsi_dump_dsidev_regs()
1658 DUMPREG(DSI_SYSCONFIG); in dsi_dump_dsidev_regs()
1659 DUMPREG(DSI_SYSSTATUS); in dsi_dump_dsidev_regs()
1660 DUMPREG(DSI_IRQSTATUS); in dsi_dump_dsidev_regs()
1661 DUMPREG(DSI_IRQENABLE); in dsi_dump_dsidev_regs()
1662 DUMPREG(DSI_CTRL); in dsi_dump_dsidev_regs()
1663 DUMPREG(DSI_COMPLEXIO_CFG1); in dsi_dump_dsidev_regs()
1664 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); in dsi_dump_dsidev_regs()
1665 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); in dsi_dump_dsidev_regs()
[all …]
Ddss.c390 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) in dss_dump_regs() macro
395 DUMPREG(DSS_REVISION); in dss_dump_regs()
396 DUMPREG(DSS_SYSCONFIG); in dss_dump_regs()
397 DUMPREG(DSS_SYSSTATUS); in dss_dump_regs()
398 DUMPREG(DSS_CONTROL); in dss_dump_regs()
402 DUMPREG(DSS_SDI_CONTROL); in dss_dump_regs()
403 DUMPREG(DSS_PLL_CONTROL); in dss_dump_regs()
404 DUMPREG(DSS_SDI_STATUS); in dss_dump_regs()
408 #undef DUMPREG in dss_dump_regs()
/drivers/gpu/drm/exynos/
Dexynos_mixer.c223 #define DUMPREG(reg_id) \ in mixer_regs_dump() macro
229 DUMPREG(MXR_STATUS); in mixer_regs_dump()
230 DUMPREG(MXR_CFG); in mixer_regs_dump()
231 DUMPREG(MXR_INT_EN); in mixer_regs_dump()
232 DUMPREG(MXR_INT_STATUS); in mixer_regs_dump()
234 DUMPREG(MXR_LAYER_CFG); in mixer_regs_dump()
235 DUMPREG(MXR_VIDEO_CFG); in mixer_regs_dump()
237 DUMPREG(MXR_GRAPHIC0_CFG); in mixer_regs_dump()
238 DUMPREG(MXR_GRAPHIC0_BASE); in mixer_regs_dump()
239 DUMPREG(MXR_GRAPHIC0_SPAN); in mixer_regs_dump()
[all …]