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Searched refs:DYN_GFX_CLK_OFF_EN (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/radeon/
Drv730d.h89 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro
Dtrinityd.h179 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro
Drv770_dpm.c134 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable()
136 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable()
173 if (RREG32(SCLK_PWRMGT_CNTL) & DYN_GFX_CLK_OFF_EN) in rv770_restore_cgcg()
177 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in rv770_restore_cgcg()
1633 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
1664 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
Dsumod.h158 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro
Dcypress_dpm.c103 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
143 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable()
145 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable()
Dr600_dpm.c245 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable()
247 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable()
Dtrinity_dpm.c445 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in trinity_gfx_clockgating_enable()
447 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in trinity_gfx_clockgating_enable()
Dsumo_dpm.c92 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in sumo_gfx_clockgating_enable()
94 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in sumo_gfx_clockgating_enable()
Drv770d.h164 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro
Dnid.h605 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro
Dsid.h257 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro
Devergreend.h143 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro
Dr600d.h1318 # define DYN_GFX_CLK_OFF_EN (1 << 10) macro
Dni_dpm.c1205 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h259 # define DYN_GFX_CLK_OFF_EN (1 << 7) macro