Searched refs:ENABLE_CONTEXT (Results 1 – 16 of 16) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| D | gmc_v6_0.c | 413 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in gmc_v6_0_gart_enable()
441 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in gmc_v6_0_gart_enable()
|
| D | gmc_v7_0.c | 533 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
563 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v7_0_gart_enable()
|
| D | gmc_v8_0.c | 658 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
688 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); in gmc_v8_0_gart_enable()
|
| /drivers/gpu/drm/radeon/ |
| D | rv770d.h | 635 #define ENABLE_CONTEXT (1 << 0) macro
|
| D | nid.h | 128 #define ENABLE_CONTEXT (1 << 0) macro
|
| D | ni.c | 1315 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cayman_pcie_gart_enable()
1339 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cayman_pcie_gart_enable()
|
| D | sid.h | 393 #define ENABLE_CONTEXT (1 << 0) macro
|
| D | cikd.h | 513 #define ENABLE_CONTEXT (1 << 0) macro
|
| D | rv770.c | 928 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in rv770_pcie_gart_enable()
|
| D | evergreend.h | 1137 #define ENABLE_CONTEXT (1 << 0) macro
|
| D | r600d.h | 574 #define ENABLE_CONTEXT (1 << 0) macro
|
| D | si.c | 4314 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in si_pcie_gart_enable()
4342 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in si_pcie_gart_enable()
|
| D | cik.c | 5512 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cik_pcie_gart_enable()
5536 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cik_pcie_gart_enable()
|
| D | r600.c | 1166 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in r600_pcie_gart_enable()
|
| D | evergreen.c | 2543 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in evergreen_pcie_gart_enable()
|
| /drivers/gpu/drm/amd/include/asic_reg/si/ |
| D | sid.h | 395 #define ENABLE_CONTEXT (1 << 0) macro
|