Home
last modified time | relevance | path

Searched refs:ENABLE_L1_TLB (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgmc_v7_0.c501 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v7_0_gart_enable()
619 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v7_0_gart_disable()
Dgmc_v8_0.c610 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); in gmc_v8_0_gart_enable()
745 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); in gmc_v8_0_gart_disable()
Dgmc_v6_0.c390 ENABLE_L1_TLB | in gmc_v6_0_gart_enable()
/drivers/gpu/drm/radeon/
Drv770.c912 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
989 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in rv770_agp_enable()
Drv770d.h465 #define ENABLE_L1_TLB (1 << 0) macro
Dnid.h179 #define ENABLE_L1_TLB (1 << 0) macro
Dsid.h475 #define ENABLE_L1_TLB (1 << 0) macro
Dcikd.h602 #define ENABLE_L1_TLB (1 << 0) macro
Devergreend.h955 #define ENABLE_L1_TLB (1 << 0) macro
Dr600d.h332 #define ENABLE_L1_TLB (1 << 0) macro
Dni.c1292 ENABLE_L1_TLB | in cayman_pcie_gart_enable()
Dr600.c1143 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1235 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in r600_agp_enable()
Devergreen.c2518 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable()
2601 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in evergreen_agp_enable()
Dsi.c4291 ENABLE_L1_TLB | in si_pcie_gart_enable()
Dcik.c5489 ENABLE_L1_TLB | in cik_pcie_gart_enable()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h477 #define ENABLE_L1_TLB (1 << 0) macro