Home
last modified time | relevance | path

Searched refs:ENABLE_L2_CACHE (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgmc_v7_0.c509 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
625 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v7_0_gart_disable()
Dgmc_v8_0.c618 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
751 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v8_0_gart_disable()
Dgmc_v6_0.c396 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in gmc_v6_0_gart_enable()
/drivers/gpu/drm/radeon/
Drv770.c906 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
983 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_agp_enable()
Drv770d.h643 #define ENABLE_L2_CACHE (1 << 0) macro
Dnid.h105 #define ENABLE_L2_CACHE (1 << 0) macro
Dsid.h370 #define ENABLE_L2_CACHE (1 << 0) macro
Dcikd.h490 #define ENABLE_L2_CACHE (1 << 0) macro
Devergreend.h1151 #define ENABLE_L2_CACHE (1 << 0) macro
Dr600d.h588 #define ENABLE_L2_CACHE (1 << 0) macro
Dni.c1298 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cayman_pcie_gart_enable()
Dr600.c1137 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1229 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_agp_enable()
Devergreen.c2512 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable()
2595 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_agp_enable()
Dsi.c4297 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in si_pcie_gart_enable()
Dcik.c5495 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cik_pcie_gart_enable()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h372 #define ENABLE_L2_CACHE (1 << 0) macro