Searched refs:ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (Results 1 – 16 of 16) sorted by relevance
398 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in gmc_v6_0_gart_enable()499 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in gmc_v6_0_gart_disable()
511 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v7_0_gart_enable()
620 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1); in gmc_v8_0_gart_enable()
907 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in rv770_pcie_gart_enable()984 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in rv770_agp_enable()
645 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
107 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
1300 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_enable()1379 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cayman_pcie_gart_disable()
374 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
494 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
1153 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
590 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro
1138 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in r600_pcie_gart_enable()1230 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in r600_agp_enable()
2513 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in evergreen_pcie_gart_enable()2596 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in evergreen_agp_enable()
4299 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_enable()4385 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
5497 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_enable()5616 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in cik_pcie_gart_disable()
376 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) macro