1 /* 2 * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef _ENA_ETH_IO_H_ 33 #define _ENA_ETH_IO_H_ 34 35 enum ena_eth_io_l3_proto_index { 36 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0, 37 38 ENA_ETH_IO_L3_PROTO_IPV4 = 8, 39 40 ENA_ETH_IO_L3_PROTO_IPV6 = 11, 41 42 ENA_ETH_IO_L3_PROTO_FCOE = 21, 43 44 ENA_ETH_IO_L3_PROTO_ROCE = 22, 45 }; 46 47 enum ena_eth_io_l4_proto_index { 48 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0, 49 50 ENA_ETH_IO_L4_PROTO_TCP = 12, 51 52 ENA_ETH_IO_L4_PROTO_UDP = 13, 53 54 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23, 55 }; 56 57 struct ena_eth_io_tx_desc { 58 /* 15:0 : length - Buffer length in bytes, must 59 * include any packet trailers that the ENA supposed 60 * to update like End-to-End CRC, Authentication GMAC 61 * etc. This length must not include the 62 * 'Push_Buffer' length. This length must not include 63 * the 4-byte added in the end for 802.3 Ethernet FCS 64 * 21:16 : req_id_hi - Request ID[15:10] 65 * 22 : reserved22 - MBZ 66 * 23 : meta_desc - MBZ 67 * 24 : phase 68 * 25 : reserved1 - MBZ 69 * 26 : first - Indicates first descriptor in 70 * transaction 71 * 27 : last - Indicates last descriptor in 72 * transaction 73 * 28 : comp_req - Indicates whether completion 74 * should be posted, after packet is transmitted. 75 * Valid only for first descriptor 76 * 30:29 : reserved29 - MBZ 77 * 31 : reserved31 - MBZ 78 */ 79 u32 len_ctrl; 80 81 /* 3:0 : l3_proto_idx - L3 protocol. This field 82 * required when l3_csum_en,l3_csum or tso_en are set. 83 * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and 84 * DF flags of the IPv4 header is 0. Otherwise must 85 * be set to 1 86 * 6:5 : reserved5 87 * 7 : tso_en - Enable TSO, For TCP only. 88 * 12:8 : l4_proto_idx - L4 protocol. This field need 89 * to be set when l4_csum_en or tso_en are set. 90 * 13 : l3_csum_en - enable IPv4 header checksum. 91 * 14 : l4_csum_en - enable TCP/UDP checksum. 92 * 15 : ethernet_fcs_dis - when set, the controller 93 * will not append the 802.3 Ethernet Frame Check 94 * Sequence to the packet 95 * 16 : reserved16 96 * 17 : l4_csum_partial - L4 partial checksum. when 97 * set to 0, the ENA calculates the L4 checksum, 98 * where the Destination Address required for the 99 * TCP/UDP pseudo-header is taken from the actual 100 * packet L3 header. when set to 1, the ENA doesn't 101 * calculate the sum of the pseudo-header, instead, 102 * the checksum field of the L4 is used instead. When 103 * TSO enabled, the checksum of the pseudo-header 104 * must not include the tcp length field. L4 partial 105 * checksum should be used for IPv6 packet that 106 * contains Routing Headers. 107 * 20:18 : reserved18 - MBZ 108 * 21 : reserved21 - MBZ 109 * 31:22 : req_id_lo - Request ID[9:0] 110 */ 111 u32 meta_ctrl; 112 113 u32 buff_addr_lo; 114 115 /* address high and header size 116 * 15:0 : addr_hi - Buffer Pointer[47:32] 117 * 23:16 : reserved16_w2 118 * 31:24 : header_length - Header length. For Low 119 * Latency Queues, this fields indicates the number 120 * of bytes written to the headers' memory. For 121 * normal queues, if packet is TCP or UDP, and longer 122 * than max_header_size, then this field should be 123 * set to the sum of L4 header offset and L4 header 124 * size(without options), otherwise, this field 125 * should be set to 0. For both modes, this field 126 * must not exceed the max_header_size. 127 * max_header_size value is reported by the Max 128 * Queues Feature descriptor 129 */ 130 u32 buff_addr_hi_hdr_sz; 131 }; 132 133 struct ena_eth_io_tx_meta_desc { 134 /* 9:0 : req_id_lo - Request ID[9:0] 135 * 11:10 : reserved10 - MBZ 136 * 12 : reserved12 - MBZ 137 * 13 : reserved13 - MBZ 138 * 14 : ext_valid - if set, offset fields in Word2 139 * are valid Also MSS High in Word 0 and bits [31:24] 140 * in Word 3 141 * 15 : reserved15 142 * 19:16 : mss_hi 143 * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1: 144 * Extended Metadata Descriptor 145 * 21 : meta_store - Store extended metadata in queue 146 * cache 147 * 22 : reserved22 - MBZ 148 * 23 : meta_desc - MBO 149 * 24 : phase 150 * 25 : reserved25 - MBZ 151 * 26 : first - Indicates first descriptor in 152 * transaction 153 * 27 : last - Indicates last descriptor in 154 * transaction 155 * 28 : comp_req - Indicates whether completion 156 * should be posted, after packet is transmitted. 157 * Valid only for first descriptor 158 * 30:29 : reserved29 - MBZ 159 * 31 : reserved31 - MBZ 160 */ 161 u32 len_ctrl; 162 163 /* 5:0 : req_id_hi 164 * 31:6 : reserved6 - MBZ 165 */ 166 u32 word1; 167 168 /* 7:0 : l3_hdr_len 169 * 15:8 : l3_hdr_off 170 * 21:16 : l4_hdr_len_in_words - counts the L4 header 171 * length in words. there is an explicit assumption 172 * that L4 header appears right after L3 header and 173 * L4 offset is based on l3_hdr_off+l3_hdr_len 174 * 31:22 : mss_lo 175 */ 176 u32 word2; 177 178 u32 reserved; 179 }; 180 181 struct ena_eth_io_tx_cdesc { 182 /* Request ID[15:0] */ 183 u16 req_id; 184 185 u8 status; 186 187 /* flags 188 * 0 : phase 189 * 7:1 : reserved1 190 */ 191 u8 flags; 192 193 u16 sub_qid; 194 195 u16 sq_head_idx; 196 }; 197 198 struct ena_eth_io_rx_desc { 199 /* In bytes. 0 means 64KB */ 200 u16 length; 201 202 /* MBZ */ 203 u8 reserved2; 204 205 /* 0 : phase 206 * 1 : reserved1 - MBZ 207 * 2 : first - Indicates first descriptor in 208 * transaction 209 * 3 : last - Indicates last descriptor in transaction 210 * 4 : comp_req 211 * 5 : reserved5 - MBO 212 * 7:6 : reserved6 - MBZ 213 */ 214 u8 ctrl; 215 216 u16 req_id; 217 218 /* MBZ */ 219 u16 reserved6; 220 221 u32 buff_addr_lo; 222 223 u16 buff_addr_hi; 224 225 /* MBZ */ 226 u16 reserved16_w3; 227 }; 228 229 /* 4-word format Note: all ethernet parsing information are valid only when 230 * last=1 231 */ 232 struct ena_eth_io_rx_cdesc_base { 233 /* 4:0 : l3_proto_idx 234 * 6:5 : src_vlan_cnt 235 * 7 : reserved7 - MBZ 236 * 12:8 : l4_proto_idx 237 * 13 : l3_csum_err - when set, either the L3 238 * checksum error detected, or, the controller didn't 239 * validate the checksum. This bit is valid only when 240 * l3_proto_idx indicates IPv4 packet 241 * 14 : l4_csum_err - when set, either the L4 242 * checksum error detected, or, the controller didn't 243 * validate the checksum. This bit is valid only when 244 * l4_proto_idx indicates TCP/UDP packet, and, 245 * ipv4_frag is not set 246 * 15 : ipv4_frag - Indicates IPv4 fragmented packet 247 * 23:16 : reserved16 248 * 24 : phase 249 * 25 : l3_csum2 - second checksum engine result 250 * 26 : first - Indicates first descriptor in 251 * transaction 252 * 27 : last - Indicates last descriptor in 253 * transaction 254 * 29:28 : reserved28 255 * 30 : buffer - 0: Metadata descriptor. 1: Buffer 256 * Descriptor was used 257 * 31 : reserved31 258 */ 259 u32 status; 260 261 u16 length; 262 263 u16 req_id; 264 265 /* 32-bit hash result */ 266 u32 hash; 267 268 u16 sub_qid; 269 270 u16 reserved; 271 }; 272 273 /* 8-word format */ 274 struct ena_eth_io_rx_cdesc_ext { 275 struct ena_eth_io_rx_cdesc_base base; 276 277 u32 buff_addr_lo; 278 279 u16 buff_addr_hi; 280 281 u16 reserved16; 282 283 u32 reserved_w6; 284 285 u32 reserved_w7; 286 }; 287 288 struct ena_eth_io_intr_reg { 289 /* 14:0 : rx_intr_delay 290 * 29:15 : tx_intr_delay 291 * 30 : intr_unmask 292 * 31 : reserved 293 */ 294 u32 intr_control; 295 }; 296 297 struct ena_eth_io_numa_node_cfg_reg { 298 /* 7:0 : numa 299 * 30:8 : reserved 300 * 31 : enabled 301 */ 302 u32 numa_cfg; 303 }; 304 305 /* tx_desc */ 306 #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0) 307 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16 308 #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16) 309 #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23 310 #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23) 311 #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24 312 #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24) 313 #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26 314 #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26) 315 #define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27 316 #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27) 317 #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28 318 #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28) 319 #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0) 320 #define ENA_ETH_IO_TX_DESC_DF_SHIFT 4 321 #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4) 322 #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7 323 #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7) 324 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8 325 #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8) 326 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13 327 #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13) 328 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14 329 #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14) 330 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15 331 #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15) 332 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17 333 #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17) 334 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22 335 #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22) 336 #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0) 337 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24 338 #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24) 339 340 /* tx_meta_desc */ 341 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0) 342 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14 343 #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14) 344 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16 345 #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16) 346 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20 347 #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20) 348 #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21 349 #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21) 350 #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23 351 #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23) 352 #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24 353 #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24) 354 #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26 355 #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26) 356 #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27 357 #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27) 358 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28 359 #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28) 360 #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0) 361 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0) 362 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8 363 #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8) 364 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16 365 #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16) 366 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22 367 #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22) 368 369 /* tx_cdesc */ 370 #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0) 371 372 /* rx_desc */ 373 #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0) 374 #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2 375 #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2) 376 #define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3 377 #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3) 378 #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4 379 #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4) 380 381 /* rx_cdesc_base */ 382 #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0) 383 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5 384 #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5) 385 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8 386 #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8) 387 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13 388 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13) 389 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14 390 #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14) 391 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15 392 #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15) 393 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24 394 #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24) 395 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25 396 #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25) 397 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26 398 #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26) 399 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27 400 #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27) 401 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30 402 #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30) 403 404 /* intr_reg */ 405 #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0) 406 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15 407 #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15) 408 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30 409 #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30) 410 411 /* numa_node_cfg_reg */ 412 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0) 413 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31 414 #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31) 415 416 #endif /*_ENA_ETH_IO_H_ */ 417