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Searched refs:EVERGREEN_GRPH_UPDATE (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/radeon/
Devergreen_reg.h160 #define EVERGREEN_GRPH_UPDATE 0x6844 macro
Devergreen.c1439 return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & in evergreen_page_flip_pending()
2841 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_stop()
2844 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in evergreen_mc_stop()
2885 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_resume()
2888 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in evergreen_mc_resume()
2896 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_resume()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h2031 #define EVERGREEN_GRPH_UPDATE 0x1a11 macro
2224 #define EVERGREEN_GRPH_UPDATE 0x1a11 macro
2352 #define EVERGREEN_GRPH_UPDATE 0x1a11 macro
/drivers/gpu/drm/amd/amdgpu/
Ddce_v6_0.c585 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in dce_v6_0_resume_mc_access()
588 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in dce_v6_0_resume_mc_access()
596 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in dce_v6_0_resume_mc_access()