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Searched refs:GATE (Results 1 – 25 of 29) sorted by relevance

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/drivers/clk/samsung/
Dclk-exynos5433.c545 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
547 GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
550 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
553 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
556 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
559 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
562 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
565 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
568 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
571 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
[all …]
Dclk-exynos5250.c484 GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0),
485 GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0),
486 GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0),
487 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0),
492 GATE(CLK_SCLK_CAM_BAYER, "sclk_cam_bayer", "div_cam_bayer",
494 GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0",
496 GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1",
498 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "div_gscl_wa",
500 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "div_gscl_wb",
503 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "div_fimd1",
[all …]
Dclk-exynos4415.c579 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
581 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
583 GATE(CLK_ASYNC_TVX, "async_tvx", "div_aclk_100", GATE_IP_LEFTBUS, 3,
585 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
587 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
591 GATE(CLK_PPMUIMAGE, "ppmuimage", "div_aclk_100", GATE_IP_IMAGE,
593 GATE(CLK_QEMDMA2, "qe_mdma2", "div_aclk_100", GATE_IP_IMAGE,
595 GATE(CLK_QEROTATOR, "qe_rotator", "div_aclk_100", GATE_IP_IMAGE,
597 GATE(CLK_SMMUMDMA2, "smmu_mdam2", "div_aclk_100", GATE_IP_IMAGE,
599 GATE(CLK_SMMUROTATOR, "smmu_rotator", "div_aclk_100", GATE_IP_IMAGE,
[all …]
Dclk-exynos3250.c442 GATE(CLK_ASYNC_G3D, "async_g3d", "div_aclk_100", GATE_IP_LEFTBUS, 6,
444 GATE(CLK_ASYNC_MFCL, "async_mfcl", "div_aclk_100", GATE_IP_LEFTBUS, 4,
446 GATE(CLK_PPMULEFT, "ppmuleft", "div_aclk_100", GATE_IP_LEFTBUS, 1,
448 GATE(CLK_GPIO_LEFT, "gpio_left", "div_aclk_100", GATE_IP_LEFTBUS, 0,
452 GATE(CLK_ASYNC_ISPMX, "async_ispmx", "div_aclk_100",
454 GATE(CLK_ASYNC_FSYSD, "async_fsysd", "div_aclk_100",
456 GATE(CLK_ASYNC_LCD0X, "async_lcd0x", "div_aclk_100",
458 GATE(CLK_ASYNC_CAMX, "async_camx", "div_aclk_100", GATE_IP_RIGHTBUS, 2,
460 GATE(CLK_PPMURIGHT, "ppmuright", "div_aclk_100", GATE_IP_RIGHTBUS, 1,
462 GATE(CLK_GPIO_RIGHT, "gpio_right", "div_aclk_100", GATE_IP_RIGHTBUS, 0,
[all …]
Dclk-exynos4.c846 GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),
847 GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),
848 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
849 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0,
851 GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0),
852 GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0),
853 GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0),
854 GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0),
855 GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0),
856 GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0),
[all …]
Dclk-exynos7.c148 GATE(ACLK_CCORE_133, "aclk_ccore_133", "dout_aclk_ccore_133",
151 GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
154 GATE(ACLK_PERIS_66, "aclk_peris_66", "dout_aclk_peris_66",
157 GATE(SCLK_AUD_PLL, "sclk_aud_pll", "dout_sclk_aud_pll",
159 GATE(SCLK_MFC_PLL_B, "sclk_mfc_pll_b", "dout_sclk_mfc_pll",
161 GATE(SCLK_MFC_PLL_A, "sclk_mfc_pll_a", "dout_sclk_mfc_pll",
163 GATE(SCLK_BUS1_PLL_B, "sclk_bus1_pll_b", "dout_sclk_bus1_pll",
165 GATE(SCLK_BUS1_PLL_A, "sclk_bus1_pll_a", "dout_sclk_bus1_pll",
167 GATE(SCLK_BUS0_PLL_B, "sclk_bus0_pll_b", "dout_sclk_bus0_pll",
169 GATE(SCLK_BUS0_PLL_A, "sclk_bus0_pll_a", "dout_sclk_bus0_pll",
[all …]
Dclk-s5pv210.c588 GATE(CLK_ROTATOR, "rotator", "dout_hclkd", CLK_GATE_IP0, 29, 0, 0),
589 GATE(CLK_FIMC2, "fimc2", "dout_hclkd", CLK_GATE_IP0, 26, 0, 0),
590 GATE(CLK_FIMC1, "fimc1", "dout_hclkd", CLK_GATE_IP0, 25, 0, 0),
591 GATE(CLK_FIMC0, "fimc0", "dout_hclkd", CLK_GATE_IP0, 24, 0, 0),
592 GATE(CLK_PDMA0, "pdma0", "dout_hclkp", CLK_GATE_IP0, 3, 0, 0),
593 GATE(CLK_MDMA, "mdma", "dout_hclkd", CLK_GATE_IP0, 2, 0, 0),
595 GATE(CLK_SROMC, "sromc", "dout_hclkp", CLK_GATE_IP1, 26, 0, 0),
596 GATE(CLK_NANDXL, "nandxl", "dout_hclkp", CLK_GATE_IP1, 24, 0, 0),
597 GATE(CLK_USB_OTG, "usb_otg", "dout_hclkp", CLK_GATE_IP1, 16, 0, 0),
598 GATE(CLK_TVENC, "tvenc", "dout_hclkd", CLK_GATE_IP1, 10, 0, 0),
[all …]
Dclk-exynos5420.c586 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
588 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
952 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
953 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
954 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
955 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
956 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
958 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
960 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
963 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
[all …]
Dclk-exynos5260.c117 GATE(AUD_SCLK_I2S, "sclk_aud_i2s", "dout_sclk_aud_i2s",
119 GATE(AUD_SCLK_PCM, "sclk_aud_pcm", "dout_sclk_aud_pcm",
121 GATE(AUD_SCLK_AUD_UART, "sclk_aud_uart", "dout_sclk_aud_uart",
124 GATE(AUD_CLK_SRAMC, "clk_sramc", "dout_aclk_aud_131", EN_IP_AUD,
126 GATE(AUD_CLK_DMAC, "clk_dmac", "dout_aclk_aud_131",
128 GATE(AUD_CLK_I2S, "clk_i2s", "dout_aclk_aud_131", EN_IP_AUD, 2, 0, 0),
129 GATE(AUD_CLK_PCM, "clk_pcm", "dout_aclk_aud_131", EN_IP_AUD, 3, 0, 0),
130 GATE(AUD_CLK_AUD_UART, "clk_aud_uart", "dout_aclk_aud_131",
287 GATE(DISP_MOUT_HDMI_PHY_PIXEL_USER, "sclk_hdmi_link_i_pixel",
290 GATE(DISP_SCLK_PIXEL, "sclk_hdmi_phy_pixel_clki",
[all …]
Dclk-exynos5410.c169 GATE(CLK_SSS, "sss", "aclk266", GATE_IP_G2D, 2, 0, 0),
170 GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
171 GATE(CLK_WDT, "wdt", "aclk66", GATE_IP_PERIS, 19, 0, 0),
172 GATE(CLK_RTC, "rtc", "aclk66", GATE_IP_PERIS, 20, 0, 0),
173 GATE(CLK_TMU, "tmu", "aclk66", GATE_IP_PERIS, 21, 0, 0),
175 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
177 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
179 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
182 GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
183 GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
[all …]
Dclk-s3c2443.c158 GATE(SCLK_HSMMC_EXT, "sclk_hsmmcext", "ext", SCLKCON, 13, 0, 0),
159 GATE(SCLK_HSMMC1, "sclk_hsmmc1", "div_hsmmc1", SCLKCON, 12, 0, 0),
160 GATE(SCLK_FIMD, "sclk_fimd", "div_fimd", SCLKCON, 10, 0, 0),
161 GATE(SCLK_I2S0, "sclk_i2s0", "mux_i2s0", SCLKCON, 9, 0, 0),
162 GATE(SCLK_UART, "sclk_uart", "div_uart", SCLKCON, 8, 0, 0),
163 GATE(SCLK_USBH, "sclk_usbhost", "div_usbhost", SCLKCON, 1, 0, 0),
164 GATE(HCLK_DRAM, "dram", "hclk", HCLKCON, 19, CLK_IGNORE_UNUSED, 0),
165 GATE(HCLK_SSMC, "ssmc", "hclk", HCLKCON, 18, CLK_IGNORE_UNUSED, 0),
166 GATE(HCLK_HSMMC1, "hsmmc1", "hclk", HCLKCON, 16, 0, 0),
167 GATE(HCLK_USBD, "usb-device", "hclk", HCLKCON, 12, 0, 0),
[all …]
Dclk-exynos5440.c67 GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0),
68 GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0),
69 GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0),
70 GATE(CLK_B_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0),
71 GATE(CLK_B_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0),
72 GATE(CLK_B_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0),
73 GATE(CLK_SATA, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0),
74 GATE(CLK_USB, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0),
75 GATE(CLK_GMAC0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0),
76 GATE(CLK_CS250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0),
[all …]
Dclk-s3c2412.c154 GATE(PCLK_WDT, "wdt", "pclk", CLKCON, 28, 0, 0),
155 GATE(PCLK_SPI, "spi", "pclk", CLKCON, 27, 0, 0),
156 GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 26, 0, 0),
157 GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 25, 0, 0),
158 GATE(PCLK_ADC, "adc", "pclk", CLKCON, 24, 0, 0),
159 GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 23, 0, 0),
160 GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 22, CLK_IGNORE_UNUSED, 0),
161 GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 21, 0, 0),
162 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 20, 0, 0),
163 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 19, 0, 0),
[all …]
Dclk-s3c2410.c120 GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0),
121 GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0),
122 GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0),
123 GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0),
124 GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0),
125 GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0),
126 GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0),
127 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),
128 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),
129 GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0),
[all …]
Dclk-s3c64xx.c53 GATE(_id, cname, pname, o, b, 0, 0)
55 GATE(_id, cname, pname, o, b, CLK_SET_RATE_PARENT, 0)
57 GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0)
/drivers/clk/rockchip/
Dclk-rk3399.c408 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
410 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
413 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
415 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
430 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
432 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
434 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
436 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
438 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0,
441 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
[all …]
Dclk-rk3368.c290 GATE(0, "apllb_core", "apllb", CLK_IGNORE_UNUSED,
292 GATE(0, "gpllb_core", "gpll", CLK_IGNORE_UNUSED,
295 GATE(0, "aplll_core", "aplll", CLK_IGNORE_UNUSED,
297 GATE(0, "gplll_core", "gpll", CLK_IGNORE_UNUSED,
314 GATE(0, "apllb_cs", "apllb", CLK_IGNORE_UNUSED,
316 GATE(0, "aplll_cs", "aplll", CLK_IGNORE_UNUSED,
318 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
329 GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3368_CLKGATE_CON(7), 10, GFLAGS),
331 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
333 GATE(0, "gpll_ddr", "gpll", 0,
[all …]
Dclk-rk3228.c210 GATE(0, "apll_ddr", "apll", CLK_IGNORE_UNUSED,
212 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
214 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
219 GATE(0, "ddrc", "ddrphy_pre", CLK_IGNORE_UNUSED,
225 GATE(0, "dpll_core", "dpll", CLK_IGNORE_UNUSED,
227 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
229 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
247 GATE(0, "hdmiphy_aclk_cpu", "hdmiphy", CLK_IGNORE_UNUSED,
249 GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
251 GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
[all …]
Dclk-rk3288.c268 GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
270 GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
300 GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
302 GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
304 GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
307 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
309 GATE(0, "gpll_ddr", "gpll", 0,
315 GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
317 GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
323 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
[all …]
Dclk-rk3188.c285 GATE(0, "gpll_armclk", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
295 GATE(0, "hclk_vepu", "aclk_vepu", 0,
300 GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
303 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
309 GATE(0, "aclk_cpu", "aclk_cpu_pre", 0,
312 GATE(0, "atclk_cpu", "pclk_cpu_pre", 0,
314 GATE(0, "pclk_cpu", "pclk_cpu_pre", 0,
316 GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
326 GATE(0, "aclk_peri", "aclk_peri_pre", 0,
343 GATE(0, "pclkin_cif0", "ext_cif0", 0,
[all …]
Dclk-rk3036.c180 GATE(0, "gpll_armclk", "gpll", CLK_IGNORE_UNUSED,
189 GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
191 GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
204 GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
205 GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
208 GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
221 GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
225 GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", 0,
229 GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", 0,
324 GATE(SCLK_I2S, "sclk_i2s", "i2s_pre", CLK_SET_RATE_PARENT,
[all …]
/drivers/clk/pistachio/
Dclk-pistachio.c22 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
23 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
24 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
25 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
26 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
27 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
28 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
29 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
30 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
31 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
[all …]
/drivers/clk/zte/
Dclk-zx296718.c473 …GATE(CPU_DBG_GATE, "dbg_wclk", "dbg_mux", TOP_CLK_GATE0, 4, CLK_SET_RATE_PARENT, …
474 …GATE(A72_GATE, "a72_coreclk", "a72_mux", TOP_CLK_GATE0, 3, CLK_SET_RATE_PARENT, …
475 …GATE(CPU_PERI_GATE, "cpu_peri", "cpu_peri_mux", TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, …
476 …GATE(A53_GATE, "a53_coreclk", "a53_mux", TOP_CLK_GATE0, 0, CLK_SET_RATE_PARENT, …
477 …GATE(SD1_WCLK, "sd1_wclk", "sd1_mux", TOP_CLK_GATE1, 13, CLK_SET_RATE_PARENT,…
478 …GATE(SD0_WCLK, "sd0_wclk", "sd0_mux", TOP_CLK_GATE1, 9, CLK_SET_RATE_PARENT, …
479 …GATE(EMMC_WCLK, "emmc_wclk", "emmc_mux_div2", TOP_CLK_GATE0, 5, CLK_SET_RATE_PARENT, …
480 …GATE(EMMC_NAND_AXI, "emmc_nand_aclk", "sys_noc_aclk", TOP_CLK_GATE1, 4, CLK_SET_RATE_PARENT, …
481 …GATE(NAND_WCLK, "nand_wclk", "nand_mux", TOP_CLK_GATE0, 1, CLK_SET_RATE_PARENT, …
482 …GATE(EMMC_NAND_AHB, "emmc_nand_hclk", "sys_noc_hclk", TOP_CLK_GATE1, 0, CLK_SET_RATE_PARENT, …
[all …]
/drivers/clk/bcm/
Dclk-kona.h54 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS)
55 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED)
56 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
57 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
58 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED)
59 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE)
61 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED)
165 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
166 FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \
167 FLAG(GATE, EXISTS), \
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/drivers/clk/tegra/
Dclk-tegra-periph.c234 #define GATE(_name, _parent_name, \ macro
794 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
795 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
796 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
797 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
798 GATE("apbdma", "clk_m", 34, 0, tegra_clk_apbdma, 0),
799 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
800 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, 0),
801 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
802 GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
[all …]

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