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Searched refs:GRL_CFG0 (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/mediatek/
Dmtk_hdmi_regs.h100 #define GRL_CFG0 0x24 macro
Dmtk_hdmi.c468 val = mtk_hdmi_read(hdmi, GRL_CFG0); in mtk_hdmi_hw_aud_set_i2s_fmt()
492 mtk_hdmi_write(hdmi, GRL_CFG0, val); in mtk_hdmi_hw_aud_set_i2s_fmt()