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Searched refs:I915_NUM_ENGINES (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_guc.h91 uint64_t submissions[I915_NUM_ENGINES];
147 uint64_t submissions[I915_NUM_ENGINES];
148 uint32_t last_seqno[I915_NUM_ENGINES];
Dintel_engine_cs.c120 GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES)); in intel_engines_init()
154 for (i = 0; i < I915_NUM_ENGINES; i++) { in intel_engines_init()
189 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); in intel_engine_init_seqno()
191 I915_NUM_ENGINES * gen8_semaphore_seqno_size); in intel_engine_init_seqno()
Dintel_ringbuffer.h58 (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size)
144 #define I915_NUM_ENGINES 5 macro
285 u32 sync_seqno[I915_NUM_ENGINES-1];
297 u64 signal_ggtt[I915_NUM_ENGINES];
399 idx += I915_NUM_ENGINES; in intel_engine_sync_index()
Di915_drv.h783 u32 semaphore_seqno[I915_NUM_ENGINES - 1];
804 u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
839 } engine[I915_NUM_ENGINES];
844 u32 rseqno[I915_NUM_ENGINES], wseqno;
855 } *active_bo[I915_NUM_ENGINES], *pinned_bo;
856 u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
857 struct i915_address_space *active_vm[I915_NUM_ENGINES];
937 } engine[I915_NUM_ENGINES];
1731 u32 hw_whitelist_count[I915_NUM_ENGINES];
1788 struct intel_engine_cs engine[I915_NUM_ENGINES];
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Di915_gpu_error.c191 for (i = 0; i < I915_NUM_ENGINES; i++) in print_error_buffers()
797 for (i = 0; i < I915_NUM_ENGINES; i++) in capture_bo()
853 for (i = 0; i < I915_NUM_ENGINES; i++) { in i915_error_generate_code()
1148 for (i = 0; i < I915_NUM_ENGINES; i++) { in i915_gem_record_rings()
Di915_gem_gtt.h213 struct i915_gem_active last_read[I915_NUM_ENGINES];
Di915_gem_context.c148 for (i = 0; i < I915_NUM_ENGINES; i++) { in i915_gem_context_free()
Di915_gem.c3854 BUILD_BUG_ON(I915_NUM_ENGINES > 16); in __busy_read_flag()
4081 for (i = 0; i < I915_NUM_ENGINES; i++) in i915_gem_object_init()
4581 for (i = 0; i < I915_NUM_ENGINES; i++) in i915_gem_load_init()
Di915_debugfs.c1284 u64 acthd[I915_NUM_ENGINES]; in i915_hangcheck_info()
1285 u32 seqno[I915_NUM_ENGINES]; in i915_hangcheck_info()
3157 offset = id * I915_NUM_ENGINES + j; in i915_semaphore_status()
3165 offset = id + (j * I915_NUM_ENGINES); in i915_semaphore_status()
Dintel_uncore.c1577 const u32 hw_engine_mask[I915_NUM_ENGINES] = { in gen6_reset_engines()
Dintel_ringbuffer.c2562 for (i = 0; i < I915_NUM_ENGINES; i++) { in intel_ring_init_semaphores()
Di915_irq.c2918 if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES) in semaphore_passed()