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Searched refs:I915_READ_FW (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_i2c.c275 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2); in gmbus_wait()
277 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); in gmbus_wait()
332 val = I915_READ_FW(GMBUS3); in gmbus_xfer_read_chunk()
Di915_irq.c736 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; in __intel_get_crtc_scanline()
738 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; in __intel_get_crtc_scanline()
830 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; in i915_get_crtc_scanoutpos()
1283 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0)); in gen8_gt_irq_ack()
1292 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1)); in gen8_gt_irq_ack()
1301 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3)); in gen8_gt_irq_ack()
1310 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2)); in gen8_gt_irq_ack()
2437 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ); in gen8_irq_handler()
Di915_gpu_error.c1324 error->forcewake = I915_READ_FW(FORCEWAKE_VLV); in i915_capture_reg_state()
1336 error->forcewake = I915_READ_FW(FORCEWAKE); in i915_capture_reg_state()
1343 error->forcewake = I915_READ_FW(FORCEWAKE_MT); in i915_capture_reg_state()
Dintel_uncore.c1632 #define done ((I915_READ_FW(reg) & mask) == value) in intel_wait_for_register_fw()
1669 ret = wait_for_us((I915_READ_FW(reg) & mask) == value, 2); in intel_wait_for_register()
Di915_debugfs.c1506 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS); in gen6_drpc_info()
2369 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK; in i915_rps_boost_info()
2370 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK; in i915_rps_boost_info()
2371 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK; in i915_rps_boost_info()
2372 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK; in i915_rps_boost_info()
Dintel_pm.c7831 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK; in gen6_check_mailbox_status()
7853 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK; in gen7_check_mailbox_status()
7883 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { in sandybridge_pcode_read()
7899 *val = I915_READ_FW(GEN6_PCODE_DATA); in sandybridge_pcode_read()
7928 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { in sandybridge_pcode_write_timeout()
Di915_drv.h3809 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) macro
3812 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)