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Searched refs:IH_RB_CNTL (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dtonga_ih.c62 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in tonga_ih_enable_interrupts()
63 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1); in tonga_ih_enable_interrupts()
79 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in tonga_ih_disable_interrupts()
80 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0); in tonga_ih_disable_interrupts()
127 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in tonga_ih_irq_init()
128 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in tonga_ih_irq_init()
131 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0); in tonga_ih_irq_init()
134 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RPTR_REARM, 1); in tonga_ih_irq_init()
215 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in tonga_ih_get_wptr()
Dsi_ih.c34 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_enable_interrupts()
39 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_enable_interrupts()
45 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_ih_disable_interrupts()
50 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_disable_interrupts()
82 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_ih_irq_init()
114 tmp = RREG32(IH_RB_CNTL); in si_ih_get_wptr()
116 WREG32(IH_RB_CNTL, tmp); in si_ih_get_wptr()
Diceland_ih.c64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in iceland_ih_enable_interrupts()
82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in iceland_ih_disable_interrupts()
128 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in iceland_ih_irq_init()
129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in iceland_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
133 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in iceland_ih_irq_init()
204 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in iceland_ih_get_wptr()
Dcz_ih.c64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); in cz_ih_enable_interrupts()
82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); in cz_ih_disable_interrupts()
128 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); in cz_ih_irq_init()
129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in cz_ih_irq_init()
130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
133 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); in cz_ih_irq_init()
204 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); in cz_ih_get_wptr()
/drivers/gpu/drm/radeon/
Dr600.c3597 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_enable_interrupts()
3602 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_enable_interrupts()
3608 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in r600_disable_interrupts()
3613 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_disable_interrupts()
3725 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_irq_init()
4059 tmp = RREG32(IH_RB_CNTL); in r600_get_ih_wptr()
4061 WREG32(IH_RB_CNTL, tmp); in r600_get_ih_wptr()
Dsi.c5915 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_enable_interrupts()
5920 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_enable_interrupts()
5926 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in si_disable_interrupts()
5931 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_disable_interrupts()
6046 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_irq_init()
6419 tmp = RREG32(IH_RB_CNTL); in si_get_ih_wptr()
6421 WREG32(IH_RB_CNTL, tmp); in si_get_ih_wptr()
Dcik.c6887 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_enable_interrupts()
6892 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_enable_interrupts()
6905 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_disable_interrupts()
6910 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_disable_interrupts()
7054 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_irq_init()
7502 tmp = RREG32(IH_RB_CNTL); in cik_get_ih_wptr()
7504 WREG32(IH_RB_CNTL, tmp); in cik_get_ih_wptr()
Dsid.h651 #define IH_RB_CNTL 0x3e00 macro
Dcikd.h803 #define IH_RB_CNTL 0x3e00 macro
Devergreend.h1220 #define IH_RB_CNTL 0x3e00 macro
Dr600d.h659 #define IH_RB_CNTL 0x3e00 macro
Devergreen.c5037 tmp = RREG32(IH_RB_CNTL); in evergreen_get_ih_wptr()
5039 WREG32(IH_RB_CNTL, tmp); in evergreen_get_ih_wptr()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h655 #define IH_RB_CNTL 0xF80 macro