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Searched refs:LC_LINK_WIDTH_RD_MASK (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/radeon/
Drv770d.h953 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
Dnid.h1102 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
Dsid.h1509 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
Dcikd.h372 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
Drv770.c2051 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
Devergreend.h1487 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
Dr600d.h904 # define LC_LINK_WIDTH_RD_MASK 0x70 macro
Dr600.c4536 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in r600_pcie_gen2_enable()
Dci_dpm.c4809 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; in ci_get_current_pcie_lane_number()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h1573 # define LC_LINK_WIDTH_RD_MASK 0x70 macro