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Searched refs:LinkLevel (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/powerplay/smumgr/
Dpolaris10_smc.c531 table->LinkLevel[i].PcieGenSpeed = in polaris10_populate_smc_link_level()
533 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in polaris10_populate_smc_link_level()
535 table->LinkLevel[i].EnabledForActivity = 1; in polaris10_populate_smc_link_level()
536 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff); in polaris10_populate_smc_link_level()
537 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5); in polaris10_populate_smc_link_level()
538 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30); in polaris10_populate_smc_link_level()
1797 table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider)); in polaris10_init_smc_table()
Dfiji_smc.c595 table->LinkLevel[i].PcieGenSpeed = in fiji_populate_smc_link_level()
597 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width( in fiji_populate_smc_link_level()
599 table->LinkLevel[i].EnabledForActivity = 1; in fiji_populate_smc_link_level()
600 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff); in fiji_populate_smc_link_level()
601 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5); in fiji_populate_smc_link_level()
602 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30); in fiji_populate_smc_link_level()
Diceland_smc.c609 table->LinkLevel[i].PcieGenSpeed = in iceland_populate_smc_link_level()
611 table->LinkLevel[i].PcieLaneCount = in iceland_populate_smc_link_level()
613 table->LinkLevel[i].EnabledForActivity = in iceland_populate_smc_link_level()
615 table->LinkLevel[i].SPC = in iceland_populate_smc_link_level()
617 table->LinkLevel[i].DownThreshold = in iceland_populate_smc_link_level()
619 table->LinkLevel[i].UpThreshold = in iceland_populate_smc_link_level()
Dtonga_smc.c414 table->LinkLevel[i].PcieGenSpeed = in tonga_populate_smc_link_level()
416 table->LinkLevel[i].PcieLaneCount = in tonga_populate_smc_link_level()
418 table->LinkLevel[i].EnabledForActivity = in tonga_populate_smc_link_level()
420 table->LinkLevel[i].SPC = in tonga_populate_smc_link_level()
422 table->LinkLevel[i].DownThreshold = in tonga_populate_smc_link_level()
424 table->LinkLevel[i].UpThreshold = in tonga_populate_smc_link_level()
/drivers/gpu/drm/amd/powerplay/inc/
Dsmu7_discrete.h325 SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK]; member
Dsmu71_discrete.h273 SMU71_Discrete_LinkLevel LinkLevel [SMU71_MAX_LEVELS_LINK]; member
Dsmu72_discrete.h245 SMU72_Discrete_LinkLevel LinkLevel[SMU72_MAX_LEVELS_LINK]; member
Dsmu73_discrete.h252 SMU73_Discrete_LinkLevel LinkLevel [SMU73_MAX_LEVELS_LINK]; member
Dsmu74_discrete.h284 SMU74_Discrete_LinkLevel LinkLevel[SMU74_MAX_LEVELS_LINK]; member
/drivers/gpu/drm/radeon/
Dsmu7_discrete.h325 SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK]; member
Dci_dpm.c2616 table->LinkLevel[i].PcieGenSpeed = in ci_populate_smc_link_level()
2618 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
2620 table->LinkLevel[i].EnabledForActivity = 1; in ci_populate_smc_link_level()
2621 table->LinkLevel[i].DownT = cpu_to_be32(5); in ci_populate_smc_link_level()
2622 table->LinkLevel[i].UpT = cpu_to_be32(30); in ci_populate_smc_link_level()
/drivers/gpu/drm/amd/amdgpu/
Dci_dpm.c2743 table->LinkLevel[i].PcieGenSpeed = in ci_populate_smc_link_level()
2745 table->LinkLevel[i].PcieLaneCount = in ci_populate_smc_link_level()
2747 table->LinkLevel[i].EnabledForActivity = 1; in ci_populate_smc_link_level()
2748 table->LinkLevel[i].DownT = cpu_to_be32(5); in ci_populate_smc_link_level()
2749 table->LinkLevel[i].UpT = cpu_to_be32(30); in ci_populate_smc_link_level()