Searched refs:MCR_RTS (Results 1 – 6 of 6) sorted by relevance
70 #define MCR_RTS 0x02 macro330 priv->line_control |= MCR_RTS; in spcp8x5_set_termios()444 priv->line_control |= MCR_RTS; in spcp8x5_tiocmset()448 priv->line_control &= ~MCR_RTS; in spcp8x5_tiocmset()475 | ((mcr & MCR_RTS) ? TIOCM_RTS : 0) in spcp8x5_tiocmget()
126 #define MCR_RTS 0x02 // Assert RTS macro
65 #define MCR_RTS 0x02 /* Assert RTS */ macro1441 mos7840_port->shadowMCR &= ~MCR_RTS; in mos7840_throttle()1482 mos7840_port->shadowMCR |= MCR_RTS; in mos7840_unthrottle()1510 | ((mcr & MCR_RTS) ? TIOCM_RTS : 0) in mos7840_tiocmget()1538 mcr &= ~MCR_RTS; in mos7840_tiocmset()1545 mcr |= MCR_RTS; in mos7840_tiocmset()1831 mos7840_port->shadowMCR |= (MCR_DTR | MCR_RTS); in mos7840_change_port_settings()
1532 status = ti_do_config(port, UMPC_SET_CLR_RTS, mcr & MCR_RTS); in restore_mcr()1927 edge_port->shadow_mcr = MCR_RTS | MCR_DTR; in edge_open()2219 edge_port->shadow_mcr &= ~MCR_RTS; in stop_read()2237 edge_port->shadow_mcr |= MCR_RTS; in restart_read()2417 mcr |= MCR_RTS; in edge_tiocmset()2424 mcr &= ~MCR_RTS; in edge_tiocmset()2451 | ((mcr & MCR_RTS) ? TIOCM_RTS: 0) /* 0x004 */ in edge_tiocmget()
1414 edge_port->shadowMCR &= ~MCR_RTS; in edge_throttle()1451 edge_port->shadowMCR |= MCR_RTS; in edge_unthrottle()1524 mcr |= MCR_RTS; in edge_tiocmset()1531 mcr &= ~MCR_RTS; in edge_tiocmset()1555 | ((mcr & MCR_RTS) ? TIOCM_RTS: 0) /* 0x004 */ in edge_tiocmget()2529 edge_port->shadowMCR |= (MCR_DTR | MCR_RTS); in change_port_settings()
197 #define MCR_RTS 0x02 /* RTS output */ macro240 #define PTT_ON (MCR_RTS|MCR_OUT2) /* activate PTT */320 outb(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2, MCR(iobase)); in fpga_reset()335 bit = (wrd & 0x80) ? (MCR_RTS | MCR_DTR) : MCR_DTR; in fpga_write()