Home
last modified time | relevance | path

Searched refs:MemoryLevel (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/powerplay/smumgr/
Diceland_smc.c1226 …rray_adress = smu_data->smu7_data.dpm_table_start + offsetof(SMU71_Discrete_DpmTable, MemoryLevel); in iceland_populate_all_memory_levels()
1228 SMU71_Discrete_MemoryLevel *levels = smu_data->smc_state_table.MemoryLevel; in iceland_populate_all_memory_levels()
1237 &(smu_data->smc_state_table.MemoryLevel[i])); in iceland_populate_all_memory_levels()
1244 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in iceland_populate_all_memory_levels()
1251 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; in iceland_populate_all_memory_levels()
1252 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); in iceland_populate_all_memory_levels()
1257 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in iceland_populate_all_memory_levels()
Dtonga_smc.c1012 offsetof(SMU72_Discrete_DpmTable, MemoryLevel); in tonga_populate_all_memory_levels()
1017 smu_data->smc_state_table.MemoryLevel; in tonga_populate_all_memory_levels()
1029 &(smu_data->smc_state_table.MemoryLevel[i])); in tonga_populate_all_memory_levels()
1035 smu_data->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in tonga_populate_all_memory_levels()
1042 smu_data->smc_state_table.MemoryLevel[0].ActivityLevel = 0x1F; in tonga_populate_all_memory_levels()
1043 CONVERT_FROM_HOST_TO_SMC_US(smu_data->smc_state_table.MemoryLevel[0].ActivityLevel); in tonga_populate_all_memory_levels()
1048 …smu_data->smc_state_table.MemoryLevel[dpm_table->mclk_table.count-1].DisplayWatermark = PPSMC_DISP… in tonga_populate_all_memory_levels()
1157 smu_data->smc_state_table.MemoryLevel[0].MinVoltage; in tonga_populate_smc_acpi_level()
Dpolaris10_smumgr.c156 graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel); in polaris10_setup_graphics_level_structure()
Dfiji_smc.c1008 offsetof(SMU73_Discrete_DpmTable, MemoryLevel); in fiji_populate_all_memory_levels()
1012 smu_data->smc_state_table.MemoryLevel; in fiji_populate_all_memory_levels()
Dpolaris10_smc.c906 offsetof(SMU74_Discrete_DpmTable, MemoryLevel); in polaris10_populate_all_memory_levels()
910 smu_data->smc_state_table.MemoryLevel; in polaris10_populate_all_memory_levels()
/drivers/gpu/drm/amd/powerplay/inc/
Dsmu7_discrete.h324 SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY]; member
Dsmu71_discrete.h272 SMU71_Discrete_MemoryLevel MemoryLevel [SMU71_MAX_LEVELS_MEMORY]; member
Dsmu72_discrete.h244 SMU72_Discrete_MemoryLevel MemoryLevel[SMU72_MAX_LEVELS_MEMORY]; member
Dsmu73_discrete.h251 SMU73_Discrete_MemoryLevel MemoryLevel [SMU73_MAX_LEVELS_MEMORY]; member
Dsmu74_discrete.h283 SMU74_Discrete_MemoryLevel MemoryLevel[SMU74_MAX_LEVELS_MEMORY]; member
/drivers/gpu/drm/radeon/
Dsmu7_discrete.h324 SMU7_Discrete_MemoryLevel MemoryLevel [SMU7_MAX_LEVELS_MEMORY]; member
Dci_dpm.c3310 offsetof(SMU7_Discrete_DpmTable, MemoryLevel); in ci_populate_all_memory_levels()
3313 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3323 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3328 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3332 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3333 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3334 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3335 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3338 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3344 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
/drivers/gpu/drm/amd/amdgpu/
Dci_dpm.c3443 offsetof(SMU7_Discrete_DpmTable, MemoryLevel); in ci_populate_all_memory_levels()
3446 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3456 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3461 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3465 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3466 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3467 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3468 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3471 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3477 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()