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Searched refs:PACKET3 (Results 1 – 21 of 21) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c1405 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_test_ring()
1430 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v6_0_ring_emit_hdp_flush()
1448 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v6_0_ring_emit_hdp_invalidate()
1462 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in gfx_v6_0_ring_emit_fence()
1465 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence()
1474 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v6_0_ring_emit_fence()
1491 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v6_0_ring_emit_ib()
1496 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v6_0_ring_emit_ib()
1498 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v6_0_ring_emit_ib()
1542 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in gfx_v6_0_ring_test_ib()
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Dgfx_v7_0.c2047 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v7_0_ring_test_ring()
2097 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
2118 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_hdp_invalidate()
2144 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v7_0_ring_emit_fence_gfx()
2156 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in gfx_v7_0_ring_emit_fence_gfx()
2185 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in gfx_v7_0_ring_emit_fence_compute()
2220 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in gfx_v7_0_ring_emit_ib_gfx()
2225 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v7_0_ring_emit_ib_gfx()
2227 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v7_0_ring_emit_ib_gfx()
2247 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in gfx_v7_0_ring_emit_ib_compute()
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Dgfx_v8_0.c773 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in gfx_v8_0_ring_test_ring()
817 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); in gfx_v8_0_ring_test_ib()
1104 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1107 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in gfx_v8_0_get_csb_buffer()
1115 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v8_0_get_csb_buffer()
1126 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v8_0_get_csb_buffer()
1158 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in gfx_v8_0_get_csb_buffer()
1161 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v8_0_get_csb_buffer()
1627 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v8_0_do_edc_gpr_workarounds()
1633 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds()
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Dvid.h105 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
109 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Dcikd.h217 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
221 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
/drivers/gpu/drm/radeon/
Dni.c1415 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit()
1421 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit()
1437 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in cayman_ring_ib_execute()
1442 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_ring_ib_execute()
1448 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in cayman_ring_ib_execute()
1458 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_ring_ib_execute()
1564 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in cayman_cp_start()
1582 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1588 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1592 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start()
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Dcik.c3504 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_test()
3560 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
3589 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3601 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3628 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in cik_fence_compute_ring_emit()
3659 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in cik_semaphore_ring_emit()
3665 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_semaphore_ring_emit()
3720 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma()
3767 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in cik_ring_ib_execute()
3770 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in cik_ring_ib_execute()
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Dsi.c3373 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_fence_ring_emit()
3376 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_fence_ring_emit()
3385 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in si_fence_ring_emit()
3404 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in si_ring_ib_execute()
3407 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in si_ring_ib_execute()
3412 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3418 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_ring_ib_execute()
3425 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in si_ring_ib_execute()
3439 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in si_ring_ib_execute()
3442 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_ring_ib_execute()
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Dr600.c2697 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start()
2842 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test()
2880 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2886 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in r600_fence_ring_emit()
2894 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2899 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in r600_fence_ring_emit()
2902 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2906 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_fence_ring_emit()
2937 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in r600_semaphore_ring_emit()
2944 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in r600_semaphore_ring_emit()
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Dr300d.h64 #define PACKET3(op, n) (CP_PACKET3 | \ macro
Dsid.h1595 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
1599 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Dcikd.h1693 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
1697 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
Devergreen.c3029 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in evergreen_ring_ib_execute()
3034 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in evergreen_ring_ib_execute()
3040 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in evergreen_ring_ib_execute()
3047 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in evergreen_ring_ib_execute()
3101 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in evergreen_cp_start()
3120 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start()
3126 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start()
3130 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in evergreen_cp_start()
Drv515d.h204 #define PACKET3(op, n) (CP_PACKET3 | \ macro
Drv770d.h988 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
Dnid.h1157 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
Dr100d.h63 #define PACKET3(op, n) (CP_PACKET3 | \ macro
Devergreend.h1543 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
Dr600d.h1587 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
Dr100.c923 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8)); in r100_copy_blit()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h1658 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
1662 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)