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Searched refs:PACKET3_SET_CONTEXT_REG (Results 1 – 15 of 15) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dvid.h341 #define PACKET3_SET_CONTEXT_REG 0x69 macro
Dcikd.h454 #define PACKET3_SET_CONTEXT_REG 0x69 macro
Dgfx_v6_0.c1691 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v6_0_cp_gfx_start()
1705 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v6_0_cp_gfx_start()
2715 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v6_0_get_csb_buffer()
2725 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in gfx_v6_0_get_csb_buffer()
Dgfx_v7_0.c2502 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v7_0_cp_gfx_start()
2510 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v7_0_cp_gfx_start()
2542 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v7_0_cp_gfx_start()
4210 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v7_0_get_csb_buffer()
4220 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v7_0_get_csb_buffer()
Dgfx_v8_0.c1115 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v8_0_get_csb_buffer()
1126 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v8_0_get_csb_buffer()
4272 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v8_0_cp_gfx_start()
4282 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in gfx_v8_0_cp_gfx_start()
/drivers/gpu/drm/radeon/
Dnid.h1272 #define PACKET3_SET_CONTEXT_REG 0x69 macro
Dsid.h1785 #define PACKET3_SET_CONTEXT_REG 0x69 macro
Dsi.c3601 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in si_cp_start()
4568 case PACKET3_SET_CONTEXT_REG: in si_vm_packet3_gfx_check()
4671 case PACKET3_SET_CONTEXT_REG: in si_vm_packet3_compute_check()
5729 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in si_get_csb_buffer()
5739 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); in si_get_csb_buffer()
Dcikd.h1930 #define PACKET3_SET_CONTEXT_REG 0x69 macro
Devergreen_cs.c2316 case PACKET3_SET_CONTEXT_REG: in evergreen_packet3_check()
3395 case PACKET3_SET_CONTEXT_REG: in evergreen_vm_packet3_check()
Devergreend.h1668 #define PACKET3_SET_CONTEXT_REG 0x69 macro
Dr600d.h1689 #define PACKET3_SET_CONTEXT_REG 0x69 macro
Dr600_cs.c1924 case PACKET3_SET_CONTEXT_REG: in r600_packet3_check()
Dcik.c4053 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in cik_cp_gfx_start()
6793 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in cik_get_csb_buffer()
6803 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in cik_get_csb_buffer()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h1848 #define PACKET3_SET_CONTEXT_REG 0x69 macro