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Searched refs:PACKET3_WAIT_REG_MEM (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dvid.h168 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dcikd.h281 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dgfx_v7_0.c2097 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
3229 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_pipeline_sync()
3289 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_vm_flush()
Dgfx_v6_0.c1947 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v6_0_ring_emit_pipeline_sync()
1992 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v6_0_ring_emit_vm_flush()
Dgfx_v8_0.c6143 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_hdp_flush()
6232 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_pipeline_sync()
6276 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_vm_flush()
/drivers/gpu/drm/radeon/
Dnid.h1194 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dr600_cs.c845 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { in r600_cs_common_vline_parse()
1751 case PACKET3_WAIT_REG_MEM: in r600_packet3_check()
Dsid.h1656 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dcikd.h1757 #define PACKET3_WAIT_REG_MEM 0x3C macro
Devergreen_cs.c2085 case PACKET3_WAIT_REG_MEM: in evergreen_packet3_check()
3388 case PACKET3_WAIT_REG_MEM: in evergreen_vm_packet3_check()
Devergreend.h1578 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dr600d.h1615 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dsi.c4561 case PACKET3_WAIT_REG_MEM: in si_vm_packet3_gfx_check()
4664 case PACKET3_WAIT_REG_MEM: in si_vm_packet3_compute_check()
5103 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in si_vm_flush()
Dni.c2712 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cayman_vm_flush()
Dcik.c3560 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
5793 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_vm_flush()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h1719 #define PACKET3_WAIT_REG_MEM 0x3C macro