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Searched refs:PFIFO (Results 1 – 8 of 8) sorted by relevance

/drivers/video/fbdev/nvidia/
Dnv_hw.c1474 NV_WR32(par->PFIFO, 0x0140 * 4, 0x00000000); in NVLoadStateExt()
1475 NV_WR32(par->PFIFO, 0x0141 * 4, 0x00000001); in NVLoadStateExt()
1476 NV_WR32(par->PFIFO, 0x0480 * 4, 0x00000000); in NVLoadStateExt()
1477 NV_WR32(par->PFIFO, 0x0494 * 4, 0x00000000); in NVLoadStateExt()
1479 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00010000); in NVLoadStateExt()
1481 NV_WR32(par->PFIFO, 0x0481 * 4, 0x00000100); in NVLoadStateExt()
1482 NV_WR32(par->PFIFO, 0x0490 * 4, 0x00000000); in NVLoadStateExt()
1483 NV_WR32(par->PFIFO, 0x0491 * 4, 0x00000000); in NVLoadStateExt()
1485 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001213); in NVLoadStateExt()
1487 NV_WR32(par->PFIFO, 0x048B * 4, 0x00001209); in NVLoadStateExt()
[all …]
Dnv_type.h159 volatile u32 __iomem *PFIFO; member
Dnv_setup.c325 par->PFIFO = par->REGS + (0x00002000 / 4); in NVCommonSetup()
/drivers/video/fbdev/riva/
Dnvreg.h105 #define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value)
106 #define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg)
107 #define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg)
108 #define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value)
109 #define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value)
110 #define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask)
Dnv_driver.c321 par->riva.PFIFO = in riva_common_setup()
Driva_hw.h448 volatile U032 __iomem *PFIFO; member
Driva_hw.c1424 LOAD_FIXED_STATE(nv3,PFIFO); in LoadStateExt()
1464 LOAD_FIXED_STATE(nv4,PFIFO); in LoadStateExt()
1510 LOAD_FIXED_STATE(nv10,PFIFO); in LoadStateExt()
/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
Dg98.fuc0s164 // tell PFIFO we unloaded
175 // if bit 30 of next channel not set, probably PFIFO is just
193 // tell PFIFO we're done