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Searched refs:PHY_REG (Results 1 – 6 of 6) sorted by relevance

/drivers/net/ethernet/intel/e1000e/
Dich8lan.h124 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ macro
126 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
127 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
134 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
135 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
136 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
137 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
138 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
153 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
154 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
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Dethtool.c1365 e1e_rphy(hw, PHY_REG(2, 21), &phy_reg); in e1000_integrated_phy_loopback()
1368 e1e_wphy(hw, PHY_REG(2, 21), phy_reg); in e1000_integrated_phy_loopback()
1373 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg); in e1000_integrated_phy_loopback()
1374 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C); in e1000_integrated_phy_loopback()
1376 e1e_rphy(hw, PHY_REG(776, 16), &phy_reg); in e1000_integrated_phy_loopback()
1377 e1e_wphy(hw, PHY_REG(776, 16), phy_reg | 0x0040); in e1000_integrated_phy_loopback()
1379 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg); in e1000_integrated_phy_loopback()
1380 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x0040); in e1000_integrated_phy_loopback()
1382 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); in e1000_integrated_phy_loopback()
1383 e1e_wphy(hw, PHY_REG(769, 20), phy_reg | 0x0400); in e1000_integrated_phy_loopback()
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Dich8lan.c1468 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
1481 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
1493 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
2241 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); in e1000_k1_gig_workaround_hv()
2247 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); in e1000_k1_gig_workaround_hv()
2424 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); in e1000_hv_phy_workarounds_ich8lan()
2537 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); in e1000_lv_jumbo_workaround_ich8lan()
2538 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); in e1000_lv_jumbo_workaround_ich8lan()
2601 e1e_rphy(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2604 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); in e1000_lv_jumbo_workaround_ich8lan()
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Dnetdev.c3095 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); in e1000_setup_rctl()
3098 e1e_wphy(hw, PHY_REG(770, 26), phy_data); in e1000_setup_rctl()
/drivers/net/ethernet/intel/e1000/
De1000_hw.h2940 #define PHY_REG(page, reg) \ macro
2944 PHY_REG(769, 17) /* Port General Configuration */
2946 PHY_REG(769, 25) /* Rate Adapter Control Register */
2949 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
2951 PHY_REG(770, 17) /* KMRN Power Management Control Register */
2953 PHY_REG(770, 18) /* KMRN Inband Control Register */
2955 PHY_REG(770, 19) /* KMRN Diagnostic register */
2958 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
2961 PHY_REG(776, 18) /* Voltage regulator control register */
2966 PHY_REG(776, 19) /* IGP3 Capability Register */
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/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
Dreg.h255 #define PHY_REG 0x02F3 macro