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Searched refs:PINMUX_CFG_REG_VAR (Results 1 – 11 of 11) sorted by relevance

/drivers/pinctrl/sh-pfc/
Dpfc-sh7734.c1828 { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
1865 { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
1900 { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
1936 { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
1973 { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
2008 { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
2048 { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
2092 { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
2128 { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
2164 { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
[all …]
Dpfc-emev2.c1594 { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
1612 { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
1624 { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
1636 { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
1661 { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
1680 { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
Dpfc-r8a7791.c5531 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5590 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5626 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5662 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5700 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5742 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5780 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5820 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5861 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5904 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7790.c4962 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4998 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5035 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5064 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5097 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5130 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5167 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5203 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5238 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5279 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7778.c2285 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2340 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
2383 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2435 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2477 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2519 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2563 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2614 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2653 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2693 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
[all …]
Dpfc-r8a7779.c3273 { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
3311 { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3349 { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3395 { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3446 { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3494 { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3540 { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3577 { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3613 { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
3656 { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
[all …]
Dpfc-r8a7794.c4471 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4525 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4565 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4600 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4640 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
4675 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
4710 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
4756 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4793 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4828 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
[all …]
Dpfc-r8a7792.c2346 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2404 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2462 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2510 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2556 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2597 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2637 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2679 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
Dsh_pfc.h130 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ macro
571 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
Dpfc-r8a7796.c2549 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2574 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2601 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Dpfc-r8a7795.c4875 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4902 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4929 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,