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Searched refs:PIPE_CONTROL_CS_STALL (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_ringbuffer.c187 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | in intel_emit_post_sync_nonzero_flush()
235 flags |= PIPE_CONTROL_CS_STALL; in gen6_render_ring_flush()
247 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; in gen6_render_ring_flush()
275 PIPE_CONTROL_CS_STALL | in gen7_render_ring_cs_stall_wa()
301 flags |= PIPE_CONTROL_CS_STALL; in gen7_render_ring_flush()
378 flags |= PIPE_CONTROL_CS_STALL; in gen8_render_ring_flush()
398 PIPE_CONTROL_CS_STALL | in gen8_render_ring_flush()
1288 PIPE_CONTROL_CS_STALL); in gen8_rcs_signal()
1437 PIPE_CONTROL_CS_STALL | in gen8_render_emit_request()
Dintel_lrc.c875 wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | in gen8_emit_flush_coherentl3_wa()
951 PIPE_CONTROL_CS_STALL | in gen8_init_indirectctx_bb()
1031 PIPE_CONTROL_CS_STALL | in gen9_init_indirectctx_bb()
1470 flags |= PIPE_CONTROL_CS_STALL; in gen8_emit_flush_render()
1540 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL); in gen8_emit_flush_render()
1615 PIPE_CONTROL_CS_STALL | in gen8_emit_request_render()
Di915_reg.h495 #define PIPE_CONTROL_CS_STALL (1<<20) macro