Home
last modified time | relevance | path

Searched refs:RADEON_CP_RB_CNTL (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/radeon/
Drs600.c467 tmp = RREG32(RADEON_CP_RB_CNTL); in rs600_asic_reset()
468 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in rs600_asic_reset()
471 WREG32(RADEON_CP_RB_CNTL, tmp); in rs600_asic_reset()
Dr300.c428 tmp = RREG32(RADEON_CP_RB_CNTL); in r300_asic_reset()
429 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in r300_asic_reset()
432 WREG32(RADEON_CP_RB_CNTL, tmp); in r300_asic_reset()
Dr100.c1172 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); in r100_cp_init()
1178 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); in r100_cp_init()
1195 WREG32(RADEON_CP_RB_CNTL, tmp); in r100_cp_init()
2571 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_asic_reset()
2572 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in r100_asic_reset()
2575 WREG32(RADEON_CP_RB_CNTL, tmp); in r100_asic_reset()
4013 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_restore_sanity()
4015 WREG32(RADEON_CP_RB_CNTL, 0); in r100_restore_sanity()
Dradeon_reg.h3297 #define RADEON_CP_RB_CNTL 0x0704 macro