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Searched refs:RB_BLKSZ (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Duvd_v5_0.c404 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in uvd_v5_0_start()
Duvd_v6_0.c503 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); in uvd_v6_0_start()
Dgfx_v8_0.c4350 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v8_0_cp_gfx_resume()
/drivers/gpu/drm/radeon/
Drv770d.h351 #define RB_BLKSZ(x) ((x) << 8) macro
Dnid.h486 #define RB_BLKSZ(x) ((x) << 8) macro
Dsid.h1248 #define RB_BLKSZ(x) ((x) << 8) macro
Dcikd.h1306 #define RB_BLKSZ(x) ((x) << 8) macro
Drv770.c1101 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in rv770_cp_load_microcode()
Devergreend.h478 #define RB_BLKSZ(x) ((x) << 8) macro
Dr600d.h197 #define RB_BLKSZ(x) ((x) << 8) macro
Dr600.c2658 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in r600_cp_load_microcode()
Devergreen.c3071 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3)); in evergreen_cp_load_microcode()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h1277 #define RB_BLKSZ(x) ((x) << 8) macro