Searched refs:REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV (Results 1 – 2 of 2) sorted by relevance
1171 #define REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV 0x00000184 macro
501 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV, in hdmi_8996_pll_set_clk_rate()