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Searched refs:REG_READ (Results 1 – 25 of 60) sorted by relevance

123

/drivers/gpu/drm/gma500/
Dcdv_device.c47 REG_READ(vga_reg); in cdv_disable_vga()
62 if (REG_READ(SDVOB) & SDVO_DETECTED) { in cdv_output_init()
64 if (REG_READ(DP_B) & DP_DETECTED) in cdv_output_init()
68 if (REG_READ(SDVOC) & SDVO_DETECTED) { in cdv_output_init()
70 if (REG_READ(DP_C) & DP_DETECTED) in cdv_output_init()
86 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; in cdv_backlight_combination_mode()
91 u32 max = REG_READ(BLC_PWM_CTL); in cdv_get_max_backlight()
109 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in cdv_get_brightness()
145 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in cdv_set_brightness()
274 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); in cdv_save_display_registers()
[all …]
Dmdfld_intel_display.c73 temp = REG_READ(map->conf); in mdfldWaitForPipeDisable()
101 temp = REG_READ(map->conf); in mdfldWaitForPipeEnable()
115 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
133 dspcntr = REG_READ(dspcntr_reg); in mdfld__intel_plane_set_alpha()
202 dspcntr = REG_READ(map->cntr); in mdfld__intel_pipe_set_base()
225 REG_READ(map->linoff); in mdfld__intel_pipe_set_base()
227 REG_READ(map->surf); in mdfld__intel_pipe_set_base()
252 temp = REG_READ(map->cntr); in mdfld_disable_crtc()
257 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_disable_crtc()
258 REG_READ(map->base); in mdfld_disable_crtc()
[all …]
Dgma_display.c88 dspcntr = REG_READ(map->cntr); in gma_pipe_set_base()
120 REG_READ(map->base); in gma_pipe_set_base()
123 REG_READ(map->base); in gma_pipe_set_base()
125 REG_READ(map->surf); in gma_pipe_set_base()
227 temp = REG_READ(map->dpll); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
238 REG_READ(map->dpll); in gma_crtc_dpms()
244 temp = REG_READ(map->cntr); in gma_crtc_dpms()
249 REG_WRITE(map->base, REG_READ(map->base)); in gma_crtc_dpms()
[all …]
Dcdv_intel_display.c143 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
155 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
161 *val = REG_READ(SB_DATA); in cdv_sb_read()
178 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
191 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
212 REG_READ(DPIO_CFG); in cdv_sb_reset()
479 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { in cdv_disable_sr()
482 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); in cdv_disable_sr()
483 REG_READ(FW_BLC_SELF); in cdv_disable_sr()
491 REG_READ(OV_OVADD); in cdv_disable_sr()
[all …]
Dpsb_intel_lvds.c77 ret = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
89 REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); in psb_intel_lvds_get_max_backlight()
201 blc_pwm_ctl = REG_READ(BLC_PWM_CTL); in psb_intel_lvds_set_backlight()
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in psb_intel_lvds_set_power()
235 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
243 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in psb_intel_lvds_set_power()
246 pp_status = REG_READ(PP_STATUS); in psb_intel_lvds_set_power()
274 lvds_priv->savePP_ON = REG_READ(LVDSPP_ON); in psb_intel_lvds_save()
275 lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF); in psb_intel_lvds_save()
276 lvds_priv->saveLVDS = REG_READ(LVDS); in psb_intel_lvds_save()
[all …]
Doaktrail_hdmi.c291 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
307 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
355 dspcntr = REG_READ(dspcntr_reg); in oaktrail_crtc_hdmi_mode_set()
361 pipeconf = REG_READ(pipeconf_reg); in oaktrail_crtc_hdmi_mode_set()
365 REG_READ(pipeconf_reg); in oaktrail_crtc_hdmi_mode_set()
368 REG_READ(PCH_PIPEBCONF); in oaktrail_crtc_hdmi_mode_set()
391 temp = REG_READ(DSPBCNTR); in oaktrail_crtc_hdmi_dpms()
394 REG_READ(DSPBCNTR); in oaktrail_crtc_hdmi_dpms()
396 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); in oaktrail_crtc_hdmi_dpms()
397 REG_READ(DSPBSURF); in oaktrail_crtc_hdmi_dpms()
[all …]
Dpsb_intel_display.c93 pfit_control = REG_READ(PFIT_CONTROL); in psb_intel_panel_fitter_pipe()
202 pipeconf = REG_READ(map->conf); in psb_intel_crtc_mode_set()
226 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
235 u32 lvds = REG_READ(LVDS); in psb_intel_crtc_mode_set()
256 REG_READ(LVDS); in psb_intel_crtc_mode_set()
261 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
268 REG_READ(map->dpll); in psb_intel_crtc_mode_set()
293 REG_READ(map->conf); in psb_intel_crtc_mode_set()
322 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get()
324 fp = REG_READ(map->fp0); in psb_intel_crtc_clock_get()
[all …]
Dpsb_lid.c40 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); in psb_lid_timer_func()
42 pp_status = REG_READ(PP_STATUS); in psb_lid_timer_func()
46 if (REG_READ(PP_STATUS) & PP_ON) { in psb_lid_timer_func()
56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); in psb_lid_timer_func()
58 pp_status = REG_READ(PP_STATUS); in psb_lid_timer_func()
Dcdv_intel_dp.c390 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
394 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_on()
404 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
408 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_vdd_off()
423 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
428 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_on()
430 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { in cdv_intel_edp_panel_on()
431 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS)); in cdv_intel_edp_panel_on()
448 pp = REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
461 REG_READ(PP_CONTROL); in cdv_intel_edp_panel_off()
[all …]
Dmdfld_dsi_dpi.c46 (REG_READ(gen_fifo_stat_reg) & DSI_FIFO_GEN_HS_DATA_FULL)) { in mdfld_wait_for_HS_DATA_FIFO()
63 while ((timeout < 20000) && (REG_READ(gen_fifo_stat_reg) in mdfld_wait_for_HS_CTRL_FIFO()
80 while ((timeout < 20000) && ((REG_READ(gen_fifo_stat_reg) & in mdfld_wait_for_DPI_CTRL_FIFO()
98 while ((timeout < 20000) && (!(REG_READ(intr_stat_reg) in mdfld_wait_for_SPL_PKG_SENT()
147 REG_READ(MIPI_DEVICE_READY_REG(pipe)); /* posted write? */ in dsi_set_pipe_plane_enable_state()
151 REG_READ(MIPI_PORT_CONTROL(pipe)); /* posted write? */ in dsi_set_pipe_plane_enable_state()
157 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in dsi_set_pipe_plane_enable_state()
158 REG_READ(dspbase_reg); in dsi_set_pipe_plane_enable_state()
573 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_turn_on()
583 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) in mdfld_dsi_dpi_turn_on()
[all …]
Dintel_i2c.c39 val = REG_READ(chan->reg); in get_clock()
49 val = REG_READ(chan->reg); in get_data()
61 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_clock()
81 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | in set_data()
Dcdv_intel_crt.c45 temp = REG_READ(reg); in cdv_intel_crt_dpms()
108 dpll_md = REG_READ(dpll_md_reg); in cdv_intel_crt_mode_set()
148 orig = hotplug_en = REG_READ(PORT_HOTPLUG_EN); in cdv_intel_crt_detect_hotplug()
162 if (!(REG_READ(PORT_HOTPLUG_EN) & in cdv_intel_crt_detect_hotplug()
169 if ((REG_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) != in cdv_intel_crt_detect_hotplug()
Dcdv_intel_lvds.c75 retval = ((REG_READ(BLC_PWM_CTL) & in cdv_intel_lvds_get_max_backlight()
183 REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in cdv_intel_lvds_set_backlight()
209 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | in cdv_intel_lvds_set_power()
212 pp_status = REG_READ(PP_STATUS); in cdv_intel_lvds_set_power()
220 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & in cdv_intel_lvds_set_power()
223 pp_status = REG_READ(PP_STATUS); in cdv_intel_lvds_set_power()
331 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); in cdv_intel_lvds_prepare()
732 lvds = REG_READ(LVDS); in cdv_intel_lvds_init()
757 pwm = REG_READ(BLC_PWM_CTL2); in cdv_intel_lvds_init()
/drivers/net/wireless/ath/ath9k/
Dar9002_calib.c87 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
122 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_iqcal_collect()
124 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_iqcal_collect()
126 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_iqcal_collect()
141 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_gaincal_collect()
143 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_gaincal_collect()
145 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9002_hw_adc_gaincal_collect()
147 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); in ar9002_hw_adc_gaincal_collect()
165 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9002_hw_adc_dccal_collect()
167 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9002_hw_adc_dccal_collect()
[all …]
Dar9003_calib.c83 if (REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL) in ar9003_hw_per_calibration()
183 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); in ar9003_hw_iqcal_collect()
185 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); in ar9003_hw_iqcal_collect()
187 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); in ar9003_hw_iqcal_collect()
271 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
288 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
293 REG_READ(ah, offset_array[i])); in ar9003_hw_iqcalibrate()
306 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0)); in ar9003_hw_iqcalibrate()
354 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); in ar9003_hw_dynamic_osdac_selection()
384 osdac_ch0 = (REG_READ(ah, AR_PHY_65NM_CH0_BB1) >> 30) & 0x3; in ar9003_hw_dynamic_osdac_selection()
[all …]
Dar9003_wow.c48 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); in ath9k_hw_set_powermode_wow_sleep()
53 if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL)) in ath9k_hw_set_powermode_wow_sleep()
56 if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) & in ath9k_hw_set_powermode_wow_sleep()
192 rval = REG_READ(ah, AR_WOW_PATTERN); in ath9k_hw_wow_wakeup()
213 rval = REG_READ(ah, AR_MAC_PCU_WOW4); in ath9k_hw_wow_wakeup()
236 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN))); in ath9k_hw_wow_wakeup()
238 AR_WOW_CLEAR_EVENTS2(REG_READ(ah, AR_MAC_PCU_WOW4))); in ath9k_hw_wow_wakeup()
256 u32 dc = REG_READ(ah, AR_DIRECT_CONNECT); in ath9k_hw_wow_wakeup()
281 wa_reg = REG_READ(ah, AR_WA); in ath9k_hw_wow_set_arwr_reg()
364 keep_alive = REG_READ(ah, AR_WOW_KEEP_ALIVE); in ath9k_hw_wow_enable()
[all …]
Dar9002_mac.c43 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { in ar9002_hw_get_isr()
44 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) in ar9002_hw_get_isr()
46 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
50 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & in ar9002_hw_get_isr()
59 isr = REG_READ(ah, AR_ISR); in ar9002_hw_get_isr()
65 isr2 = REG_READ(ah, AR_ISR_S2); in ar9002_hw_get_isr()
88 isr = REG_READ(ah, AR_ISR_RAC); in ar9002_hw_get_isr()
109 s0_s = REG_READ(ah, AR_ISR_S0_S); in ar9002_hw_get_isr()
110 s1_s = REG_READ(ah, AR_ISR_S1_S); in ar9002_hw_get_isr()
112 s0_s = REG_READ(ah, AR_ISR_S0); in ar9002_hw_get_isr()
[all …]
Dar9002_phy.c76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar9002_hw_set_channel()
224 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar9002_hw_spur_mitigate()
297 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), in ar9002_olc_init()
335 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); in ar9002_hw_do_getnf()
338 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
345 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); in ar9002_hw_do_getnf()
348 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
382 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_get()
399 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9002_hw_antdiv_comb_conf_set()
[all …]
Dar9003_mci.c39 if (!(REG_READ(ah, address) & bit_position)) { in ar9003_mci_wait_for_interrupt()
71 REG_READ(ah, AR_MCI_INTERRUPT_RAW), in ar9003_mci_wait_for_interrupt()
72 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); in ar9003_mci_wait_for_interrupt()
232 saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN); in ar9003_mci_prep_interface()
236 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); in ar9003_mci_prep_interface()
238 REG_READ(ah, AR_MCI_INTERRUPT_RAW)); in ar9003_mci_prep_interface()
351 intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); in ar9003_mci_check_int()
375 rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); in ar9003_mci_get_isr()
376 raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW); in ar9003_mci_get_isr()
387 mci->cont_status = REG_READ(ah, AR_MCI_CONT_STATUS); in ar9003_mci_get_isr()
[all …]
Dmac.c48 return REG_READ(ah, AR_QTXDP(q)); in ath9k_hw_gettxbuf()
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; in ath9k_hw_numtxpending()
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) in ath9k_hw_numtxpending()
114 txcfg = REG_READ(ah, AR_TXCFG); in ath9k_hw_updatetxtriglevel()
652 reg = REG_READ(ah, AR_OBS_BUS_1); in ath9k_hw_setrxabort()
709 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) in ath9k_hw_stopdmarecv()
713 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0; in ath9k_hw_stopdmarecv()
729 REG_READ(ah, AR_CR), in ath9k_hw_stopdmarecv()
730 REG_READ(ah, AR_DIAG_SW), in ath9k_hw_stopdmarecv()
731 REG_READ(ah, AR_DMADBG_7)); in ath9k_hw_stopdmarecv()
[all …]
Dar9003_phy.c644 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); in ar9003_hw_set_channel_regs()
662 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); in ar9003_hw_set_channel_regs()
687 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_init_bb()
730 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); in ar9003_hw_override_ini()
748 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) in ar9003_hw_override_ini()
1085 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_rfbus_done()
1379 nf = MS(REG_READ(ah, ah->nf_regs[i]), in ar9003_hw_do_getnf()
1386 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), in ar9003_hw_do_getnf()
1436 val = REG_READ(ah, AR_PHY_SFCORR); in ar9003_hw_ani_cache_ini_regs()
1441 val = REG_READ(ah, AR_PHY_SFCORR_LOW); in ar9003_hw_ani_cache_ini_regs()
[all …]
Dar9003_mac.c195 async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE); in ar9003_hw_get_isr()
198 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) in ar9003_hw_get_isr()
200 isr = REG_READ(ah, AR_ISR); in ar9003_hw_get_isr()
204 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT; in ar9003_hw_get_isr()
214 isr2 = REG_READ(ah, AR_ISR_S2); in ar9003_hw_get_isr()
240 isr = REG_READ(ah, AR_ISR_RAC); in ar9003_hw_get_isr()
268 s0 = REG_READ(ah, AR_ISR_S0); in ar9003_hw_get_isr()
270 s1 = REG_READ(ah, AR_ISR_S1); in ar9003_hw_get_isr()
282 s5 = REG_READ(ah, AR_ISR_S5_S); in ar9003_hw_get_isr()
284 s5 = REG_READ(ah, AR_ISR_S5); in ar9003_hw_get_isr()
[all …]
Dhw.c84 if ((REG_READ(ah, reg) & mask) == val) in ath9k_hw_wait()
92 timeout, reg, REG_READ(ah, reg), mask, val); in ath9k_hw_wait()
267 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
285 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; in ath9k_hw_read_revisions()
288 val = REG_READ(ah, AR_SREV); in ath9k_hw_read_revisions()
352 regHold[i] = REG_READ(ah, addr); in ath9k_hw_chip_test()
356 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
367 rdData = REG_READ(ah, addr); in ath9k_hw_chip_test()
594 ah->WARegVal = REG_READ(ah, AR_WA); in __ath9k_hw_init()
625 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); in __ath9k_hw_init()
[all …]
Dar5008_phy.c215 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); in ar5008_hw_set_channel()
446 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar5008_hw_spur_mitigate()
567 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_init_bb()
614 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); in ar5008_hw_init_chain_masks()
637 val = REG_READ(ah, AR_PCU_MISC_MODE2) & in ar5008_hw_override_ini()
664 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); in ar5008_hw_override_ini()
677 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & in ar5008_hw_set_channel_regs()
878 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar5008_hw_rfbus_done()
1124 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); in ar5008_hw_do_getnf()
1127 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); in ar5008_hw_do_getnf()
[all …]
/drivers/net/wireless/ath/
Dhw.c23 #define REG_READ (common->ops->read) macro
124 id1 = REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_SADH_MASK; in ath_hw_setbssidmask()
151 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
152 busy = REG_READ(ah, AR_RCCNT); in ath_hw_cycle_counters_update()
153 rx = REG_READ(ah, AR_RFCNT); in ath_hw_cycle_counters_update()
154 tx = REG_READ(ah, AR_TFCNT); in ath_hw_cycle_counters_update()

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