Searched refs:RLC_CNTL (Results 1 – 11 of 11) sorted by relevance
| /drivers/gpu/drm/amd/amdgpu/ |
| D | gfx_v6_0.c | 2206 tmp = RREG32(RLC_CNTL); in gfx_v6_0_update_rlc()
2208 WREG32(RLC_CNTL, rlc); in gfx_v6_0_update_rlc()
2215 orig = data = RREG32(RLC_CNTL); in gfx_v6_0_halt_rlc()
2219 WREG32(RLC_CNTL, data); in gfx_v6_0_halt_rlc()
2229 WREG32(RLC_CNTL, 0); in gfx_v6_0_rlc_stop()
2237 WREG32(RLC_CNTL, RLC_ENABLE); in gfx_v6_0_rlc_start()
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| D | gfx_v8_0.c | 4040 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v8_0_rlc_stop()
4057 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v8_0_rlc_start()
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| /drivers/gpu/drm/radeon/ |
| D | si.c | 5201 orig = data = RREG32(RLC_CNTL); in si_halt_rlc()
5205 WREG32(RLC_CNTL, data); in si_halt_rlc()
5217 tmp = RREG32(RLC_CNTL); in si_update_rlc()
5219 WREG32(RLC_CNTL, rlc); in si_update_rlc()
5813 WREG32(RLC_CNTL, 0); in si_rlc_stop()
5822 WREG32(RLC_CNTL, RLC_ENABLE); in si_rlc_start()
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| D | r600.c | 1699 WREG32(RLC_CNTL, 0); in r600_gpu_soft_reset()
1831 WREG32(RLC_CNTL, 0); in r600_gpu_pci_config_reset()
3547 WREG32(RLC_CNTL, 0); in r600_rlc_stop()
3552 WREG32(RLC_CNTL, RLC_ENABLE); in r600_rlc_start()
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| D | sid.h | 1300 #define RLC_CNTL 0xC300 macro
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| D | cik.c | 5872 tmp = RREG32(RLC_CNTL); in cik_update_rlc()
5874 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
5881 orig = data = RREG32(RLC_CNTL); in cik_halt_rlc()
5887 WREG32(RLC_CNTL, data); in cik_halt_rlc()
5939 WREG32(RLC_CNTL, 0); in cik_rlc_stop()
5955 WREG32(RLC_CNTL, RLC_ENABLE); in cik_rlc_start()
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| D | cikd.h | 1395 #define RLC_CNTL 0xC300 macro
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| D | evergreend.h | 384 #define RLC_CNTL 0x3f00 macro
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| D | r600d.h | 685 #define RLC_CNTL 0x3f00 macro
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| D | evergreen.c | 4470 WREG32(RLC_CNTL, mask); in evergreen_rlc_start()
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| /drivers/gpu/drm/amd/include/asic_reg/si/ |
| D | sid.h | 1329 #define RLC_CNTL 0x30C0 macro
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