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1  /***************************************************************************
2  *
3  * Copyright (C) 2007-2010 SMSC
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License
7  * as published by the Free Software Foundation; either version 2
8  * of the License, or (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, see <http://www.gnu.org/licenses/>.
17  *
18  *****************************************************************************/
19 
20 #ifndef _SMSC75XX_H
21 #define _SMSC75XX_H
22 
23 /* Tx command words */
24 #define TX_CMD_A_LSO			(0x08000000)
25 #define TX_CMD_A_IPE			(0x04000000)
26 #define TX_CMD_A_TPE			(0x02000000)
27 #define TX_CMD_A_IVTG			(0x01000000)
28 #define TX_CMD_A_RVTG			(0x00800000)
29 #define TX_CMD_A_FCS			(0x00400000)
30 #define TX_CMD_A_LEN			(0x000FFFFF)
31 
32 #define TX_CMD_B_MSS			(0x3FFF0000)
33 #define TX_CMD_B_MSS_SHIFT		(16)
34 #define TX_MSS_MIN			((u16)8)
35 #define TX_CMD_B_VTAG			(0x0000FFFF)
36 
37 /* Rx command words */
38 #define RX_CMD_A_ICE			(0x80000000)
39 #define RX_CMD_A_TCE			(0x40000000)
40 #define RX_CMD_A_IPV			(0x20000000)
41 #define RX_CMD_A_PID			(0x18000000)
42 #define RX_CMD_A_PID_NIP		(0x00000000)
43 #define RX_CMD_A_PID_TCP		(0x08000000)
44 #define RX_CMD_A_PID_UDP		(0x10000000)
45 #define RX_CMD_A_PID_PP			(0x18000000)
46 #define RX_CMD_A_PFF			(0x04000000)
47 #define RX_CMD_A_BAM			(0x02000000)
48 #define RX_CMD_A_MAM			(0x01000000)
49 #define RX_CMD_A_FVTG			(0x00800000)
50 #define RX_CMD_A_RED			(0x00400000)
51 #define RX_CMD_A_RWT			(0x00200000)
52 #define RX_CMD_A_RUNT			(0x00100000)
53 #define RX_CMD_A_LONG			(0x00080000)
54 #define RX_CMD_A_RXE			(0x00040000)
55 #define RX_CMD_A_DRB			(0x00020000)
56 #define RX_CMD_A_FCS			(0x00010000)
57 #define RX_CMD_A_UAM			(0x00008000)
58 #define RX_CMD_A_LCSM			(0x00004000)
59 #define RX_CMD_A_LEN			(0x00003FFF)
60 
61 #define RX_CMD_B_CSUM			(0xFFFF0000)
62 #define RX_CMD_B_CSUM_SHIFT		(16)
63 #define RX_CMD_B_VTAG			(0x0000FFFF)
64 
65 /* SCSRs */
66 #define ID_REV				(0x0000)
67 
68 #define FPGA_REV			(0x0004)
69 
70 #define BOND_CTL			(0x0008)
71 
72 #define INT_STS				(0x000C)
73 #define INT_STS_RDFO_INT		(0x00400000)
74 #define INT_STS_TXE_INT			(0x00200000)
75 #define INT_STS_MACRTO_INT		(0x00100000)
76 #define INT_STS_TX_DIS_INT		(0x00080000)
77 #define INT_STS_RX_DIS_INT		(0x00040000)
78 #define INT_STS_PHY_INT_		(0x00020000)
79 #define INT_STS_MAC_ERR_INT		(0x00008000)
80 #define INT_STS_TDFU			(0x00004000)
81 #define INT_STS_TDFO			(0x00002000)
82 #define INT_STS_GPIOS			(0x00000FFF)
83 #define INT_STS_CLEAR_ALL		(0xFFFFFFFF)
84 
85 #define HW_CFG				(0x0010)
86 #define HW_CFG_SMDET_STS		(0x00008000)
87 #define HW_CFG_SMDET_EN			(0x00004000)
88 #define HW_CFG_EEM			(0x00002000)
89 #define HW_CFG_RST_PROTECT		(0x00001000)
90 #define HW_CFG_PORT_SWAP		(0x00000800)
91 #define HW_CFG_PHY_BOOST		(0x00000600)
92 #define HW_CFG_PHY_BOOST_NORMAL		(0x00000000)
93 #define HW_CFG_PHY_BOOST_4		(0x00002000)
94 #define HW_CFG_PHY_BOOST_8		(0x00004000)
95 #define HW_CFG_PHY_BOOST_12		(0x00006000)
96 #define HW_CFG_LEDB			(0x00000100)
97 #define HW_CFG_BIR			(0x00000080)
98 #define HW_CFG_SBP			(0x00000040)
99 #define HW_CFG_IME			(0x00000020)
100 #define HW_CFG_MEF			(0x00000010)
101 #define HW_CFG_ETC			(0x00000008)
102 #define HW_CFG_BCE			(0x00000004)
103 #define HW_CFG_LRST			(0x00000002)
104 #define HW_CFG_SRST			(0x00000001)
105 
106 #define PMT_CTL				(0x0014)
107 #define PMT_CTL_PHY_PWRUP		(0x00000400)
108 #define PMT_CTL_RES_CLR_WKP_EN		(0x00000100)
109 #define PMT_CTL_DEV_RDY			(0x00000080)
110 #define PMT_CTL_SUS_MODE		(0x00000060)
111 #define PMT_CTL_SUS_MODE_0		(0x00000000)
112 #define PMT_CTL_SUS_MODE_1		(0x00000020)
113 #define PMT_CTL_SUS_MODE_2		(0x00000040)
114 #define PMT_CTL_SUS_MODE_3		(0x00000060)
115 #define PMT_CTL_PHY_RST			(0x00000010)
116 #define PMT_CTL_WOL_EN			(0x00000008)
117 #define PMT_CTL_ED_EN			(0x00000004)
118 #define PMT_CTL_WUPS			(0x00000003)
119 #define PMT_CTL_WUPS_NO			(0x00000000)
120 #define PMT_CTL_WUPS_ED			(0x00000001)
121 #define PMT_CTL_WUPS_WOL		(0x00000002)
122 #define PMT_CTL_WUPS_MULTI		(0x00000003)
123 
124 #define LED_GPIO_CFG			(0x0018)
125 #define LED_GPIO_CFG_LED2_FUN_SEL	(0x80000000)
126 #define LED_GPIO_CFG_LED10_FUN_SEL	(0x40000000)
127 #define LED_GPIO_CFG_LEDGPIO_EN		(0x0000F000)
128 #define LED_GPIO_CFG_LEDGPIO_EN_0	(0x00001000)
129 #define LED_GPIO_CFG_LEDGPIO_EN_1	(0x00002000)
130 #define LED_GPIO_CFG_LEDGPIO_EN_2	(0x00004000)
131 #define LED_GPIO_CFG_LEDGPIO_EN_3	(0x00008000)
132 #define LED_GPIO_CFG_GPBUF		(0x00000F00)
133 #define LED_GPIO_CFG_GPBUF_0		(0x00000100)
134 #define LED_GPIO_CFG_GPBUF_1		(0x00000200)
135 #define LED_GPIO_CFG_GPBUF_2		(0x00000400)
136 #define LED_GPIO_CFG_GPBUF_3		(0x00000800)
137 #define LED_GPIO_CFG_GPDIR		(0x000000F0)
138 #define LED_GPIO_CFG_GPDIR_0		(0x00000010)
139 #define LED_GPIO_CFG_GPDIR_1		(0x00000020)
140 #define LED_GPIO_CFG_GPDIR_2		(0x00000040)
141 #define LED_GPIO_CFG_GPDIR_3		(0x00000080)
142 #define LED_GPIO_CFG_GPDATA		(0x0000000F)
143 #define LED_GPIO_CFG_GPDATA_0		(0x00000001)
144 #define LED_GPIO_CFG_GPDATA_1		(0x00000002)
145 #define LED_GPIO_CFG_GPDATA_2		(0x00000004)
146 #define LED_GPIO_CFG_GPDATA_3		(0x00000008)
147 
148 #define GPIO_CFG			(0x001C)
149 #define GPIO_CFG_SHIFT			(24)
150 #define GPIO_CFG_GPEN			(0xFF000000)
151 #define GPIO_CFG_GPBUF			(0x00FF0000)
152 #define GPIO_CFG_GPDIR			(0x0000FF00)
153 #define GPIO_CFG_GPDATA			(0x000000FF)
154 
155 #define GPIO_WAKE			(0x0020)
156 #define GPIO_WAKE_PHY_LINKUP_EN		(0x80000000)
157 #define GPIO_WAKE_POL			(0x0FFF0000)
158 #define GPIO_WAKE_POL_SHIFT		(16)
159 #define GPIO_WAKE_WK			(0x00000FFF)
160 
161 #define DP_SEL				(0x0024)
162 #define DP_SEL_DPRDY			(0x80000000)
163 #define DP_SEL_RSEL			(0x0000000F)
164 #define DP_SEL_URX			(0x00000000)
165 #define DP_SEL_VHF			(0x00000001)
166 #define DP_SEL_VHF_HASH_LEN		(16)
167 #define DP_SEL_VHF_VLAN_LEN		(128)
168 #define DP_SEL_LSO_HEAD			(0x00000002)
169 #define DP_SEL_FCT_RX			(0x00000003)
170 #define DP_SEL_FCT_TX			(0x00000004)
171 #define DP_SEL_DESCRIPTOR		(0x00000005)
172 #define DP_SEL_WOL			(0x00000006)
173 
174 #define DP_CMD				(0x0028)
175 #define DP_CMD_WRITE			(0x01)
176 #define DP_CMD_READ			(0x00)
177 
178 #define DP_ADDR				(0x002C)
179 
180 #define DP_DATA				(0x0030)
181 
182 #define BURST_CAP			(0x0034)
183 #define BURST_CAP_MASK			(0x0000000F)
184 
185 #define INT_EP_CTL			(0x0038)
186 #define INT_EP_CTL_INTEP_ON		(0x80000000)
187 #define INT_EP_CTL_RDFO_EN		(0x00400000)
188 #define INT_EP_CTL_TXE_EN		(0x00200000)
189 #define INT_EP_CTL_MACROTO_EN		(0x00100000)
190 #define INT_EP_CTL_TX_DIS_EN		(0x00080000)
191 #define INT_EP_CTL_RX_DIS_EN		(0x00040000)
192 #define INT_EP_CTL_PHY_EN_		(0x00020000)
193 #define INT_EP_CTL_MAC_ERR_EN		(0x00008000)
194 #define INT_EP_CTL_TDFU_EN		(0x00004000)
195 #define INT_EP_CTL_TDFO_EN		(0x00002000)
196 #define INT_EP_CTL_RX_FIFO_EN		(0x00001000)
197 #define INT_EP_CTL_GPIOX_EN		(0x00000FFF)
198 
199 #define BULK_IN_DLY			(0x003C)
200 #define BULK_IN_DLY_MASK		(0xFFFF)
201 
202 #define E2P_CMD				(0x0040)
203 #define E2P_CMD_BUSY			(0x80000000)
204 #define E2P_CMD_MASK			(0x70000000)
205 #define E2P_CMD_READ			(0x00000000)
206 #define E2P_CMD_EWDS			(0x10000000)
207 #define E2P_CMD_EWEN			(0x20000000)
208 #define E2P_CMD_WRITE			(0x30000000)
209 #define E2P_CMD_WRAL			(0x40000000)
210 #define E2P_CMD_ERASE			(0x50000000)
211 #define E2P_CMD_ERAL			(0x60000000)
212 #define E2P_CMD_RELOAD			(0x70000000)
213 #define E2P_CMD_TIMEOUT			(0x00000400)
214 #define E2P_CMD_LOADED			(0x00000200)
215 #define E2P_CMD_ADDR			(0x000001FF)
216 
217 #define MAX_EEPROM_SIZE			(512)
218 
219 #define E2P_DATA			(0x0044)
220 #define E2P_DATA_MASK_			(0x000000FF)
221 
222 #define RFE_CTL				(0x0060)
223 #define RFE_CTL_TCPUDP_CKM		(0x00001000)
224 #define RFE_CTL_IP_CKM			(0x00000800)
225 #define RFE_CTL_AB			(0x00000400)
226 #define RFE_CTL_AM			(0x00000200)
227 #define RFE_CTL_AU			(0x00000100)
228 #define RFE_CTL_VS			(0x00000080)
229 #define RFE_CTL_UF			(0x00000040)
230 #define RFE_CTL_VF			(0x00000020)
231 #define RFE_CTL_SPF			(0x00000010)
232 #define RFE_CTL_MHF			(0x00000008)
233 #define RFE_CTL_DHF			(0x00000004)
234 #define RFE_CTL_DPF			(0x00000002)
235 #define RFE_CTL_RST_RF			(0x00000001)
236 
237 #define VLAN_TYPE			(0x0064)
238 #define VLAN_TYPE_MASK			(0x0000FFFF)
239 
240 #define FCT_RX_CTL			(0x0090)
241 #define FCT_RX_CTL_EN			(0x80000000)
242 #define FCT_RX_CTL_RST			(0x40000000)
243 #define FCT_RX_CTL_SBF			(0x02000000)
244 #define FCT_RX_CTL_OVERFLOW		(0x01000000)
245 #define FCT_RX_CTL_FRM_DROP		(0x00800000)
246 #define FCT_RX_CTL_RX_NOT_EMPTY		(0x00400000)
247 #define FCT_RX_CTL_RX_EMPTY		(0x00200000)
248 #define FCT_RX_CTL_RX_DISABLED		(0x00100000)
249 #define FCT_RX_CTL_RXUSED		(0x0000FFFF)
250 
251 #define FCT_TX_CTL			(0x0094)
252 #define FCT_TX_CTL_EN			(0x80000000)
253 #define FCT_TX_CTL_RST			(0x40000000)
254 #define FCT_TX_CTL_TX_NOT_EMPTY		(0x00400000)
255 #define FCT_TX_CTL_TX_EMPTY		(0x00200000)
256 #define FCT_TX_CTL_TX_DISABLED		(0x00100000)
257 #define FCT_TX_CTL_TXUSED		(0x0000FFFF)
258 
259 #define FCT_RX_FIFO_END			(0x0098)
260 #define FCT_RX_FIFO_END_MASK		(0x0000007F)
261 
262 #define FCT_TX_FIFO_END			(0x009C)
263 #define FCT_TX_FIFO_END_MASK		(0x0000003F)
264 
265 #define FCT_FLOW			(0x00A0)
266 #define FCT_FLOW_THRESHOLD_OFF		(0x00007F00)
267 #define FCT_FLOW_THRESHOLD_OFF_SHIFT	(8)
268 #define FCT_FLOW_THRESHOLD_ON		(0x0000007F)
269 
270 /* MAC CSRs */
271 #define MAC_CR				(0x100)
272 #define MAC_CR_ADP			(0x00002000)
273 #define MAC_CR_ADD			(0x00001000)
274 #define MAC_CR_ASD			(0x00000800)
275 #define MAC_CR_INT_LOOP			(0x00000400)
276 #define MAC_CR_BOLMT			(0x000000C0)
277 #define MAC_CR_FDPX			(0x00000008)
278 #define MAC_CR_CFG			(0x00000006)
279 #define MAC_CR_CFG_10			(0x00000000)
280 #define MAC_CR_CFG_100			(0x00000002)
281 #define MAC_CR_CFG_1000			(0x00000004)
282 #define MAC_CR_RST			(0x00000001)
283 
284 #define MAC_RX				(0x104)
285 #define MAC_RX_MAX_SIZE			(0x3FFF0000)
286 #define MAC_RX_MAX_SIZE_SHIFT		(16)
287 #define MAC_RX_FCS_STRIP		(0x00000010)
288 #define MAC_RX_FSE			(0x00000004)
289 #define MAC_RX_RXD			(0x00000002)
290 #define MAC_RX_RXEN			(0x00000001)
291 
292 #define MAC_TX				(0x108)
293 #define MAC_TX_BFCS			(0x00000004)
294 #define MAC_TX_TXD			(0x00000002)
295 #define MAC_TX_TXEN			(0x00000001)
296 
297 #define FLOW				(0x10C)
298 #define FLOW_FORCE_FC			(0x80000000)
299 #define FLOW_TX_FCEN			(0x40000000)
300 #define FLOW_RX_FCEN			(0x20000000)
301 #define FLOW_FPF			(0x10000000)
302 #define FLOW_PAUSE_TIME			(0x0000FFFF)
303 
304 #define RAND_SEED			(0x110)
305 #define RAND_SEED_MASK			(0x0000FFFF)
306 
307 #define ERR_STS				(0x114)
308 #define ERR_STS_FCS_ERR			(0x00000100)
309 #define ERR_STS_LFRM_ERR		(0x00000080)
310 #define ERR_STS_RUNT_ERR		(0x00000040)
311 #define ERR_STS_COLLISION_ERR		(0x00000010)
312 #define ERR_STS_ALIGN_ERR		(0x00000008)
313 #define ERR_STS_URUN_ERR		(0x00000004)
314 
315 #define RX_ADDRH			(0x118)
316 #define RX_ADDRH_MASK			(0x0000FFFF)
317 
318 #define RX_ADDRL			(0x11C)
319 
320 #define MII_ACCESS			(0x120)
321 #define MII_ACCESS_PHY_ADDR		(0x0000F800)
322 #define MII_ACCESS_PHY_ADDR_SHIFT	(11)
323 #define MII_ACCESS_REG_ADDR		(0x000007C0)
324 #define MII_ACCESS_REG_ADDR_SHIFT	(6)
325 #define MII_ACCESS_READ			(0x00000000)
326 #define MII_ACCESS_WRITE		(0x00000002)
327 #define MII_ACCESS_BUSY			(0x00000001)
328 
329 #define MII_DATA			(0x124)
330 #define MII_DATA_MASK			(0x0000FFFF)
331 
332 #define WUCSR				(0x140)
333 #define WUCSR_PFDA_FR			(0x00000080)
334 #define WUCSR_WUFR			(0x00000040)
335 #define WUCSR_MPR			(0x00000020)
336 #define WUCSR_BCAST_FR			(0x00000010)
337 #define WUCSR_PFDA_EN			(0x00000008)
338 #define WUCSR_WUEN			(0x00000004)
339 #define WUCSR_MPEN			(0x00000002)
340 #define WUCSR_BCST_EN			(0x00000001)
341 
342 #define WUF_CFGX			(0x144)
343 #define WUF_CFGX_EN			(0x80000000)
344 #define WUF_CFGX_ATYPE			(0x03000000)
345 #define WUF_CFGX_ATYPE_UNICAST		(0x00000000)
346 #define WUF_CFGX_ATYPE_MULTICAST	(0x02000000)
347 #define WUF_CFGX_ATYPE_ALL		(0x03000000)
348 #define WUF_CFGX_PATTERN_OFFSET		(0x007F0000)
349 #define WUF_CFGX_PATTERN_OFFSET_SHIFT	(16)
350 #define WUF_CFGX_CRC16			(0x0000FFFF)
351 #define WUF_NUM				(8)
352 
353 #define WUF_MASKX			(0x170)
354 #define WUF_MASKX_AVALID		(0x80000000)
355 #define WUF_MASKX_ATYPE			(0x40000000)
356 
357 #define ADDR_FILTX			(0x300)
358 #define ADDR_FILTX_FB_VALID		(0x80000000)
359 #define ADDR_FILTX_FB_TYPE		(0x40000000)
360 #define ADDR_FILTX_FB_ADDRHI		(0x0000FFFF)
361 #define ADDR_FILTX_SB_ADDRLO		(0xFFFFFFFF)
362 
363 #define WUCSR2				(0x500)
364 #define WUCSR2_NS_RCD			(0x00000040)
365 #define WUCSR2_ARP_RCD			(0x00000020)
366 #define WUCSR2_TCPSYN_RCD		(0x00000010)
367 #define WUCSR2_NS_OFFLOAD		(0x00000004)
368 #define WUCSR2_ARP_OFFLOAD		(0x00000002)
369 #define WUCSR2_TCPSYN_OFFLOAD		(0x00000001)
370 
371 #define WOL_FIFO_STS			(0x504)
372 
373 #define IPV6_ADDRX			(0x510)
374 
375 #define IPV4_ADDRX			(0x590)
376 
377 
378 /* Vendor-specific PHY Definitions */
379 
380 /* Mode Control/Status Register */
381 #define PHY_MODE_CTRL_STS		(17)
382 #define MODE_CTRL_STS_EDPWRDOWN		((u16)0x2000)
383 #define MODE_CTRL_STS_ENERGYON		((u16)0x0002)
384 
385 #define PHY_INT_SRC			(29)
386 #define PHY_INT_SRC_ENERGY_ON		((u16)0x0080)
387 #define PHY_INT_SRC_ANEG_COMP		((u16)0x0040)
388 #define PHY_INT_SRC_REMOTE_FAULT	((u16)0x0020)
389 #define PHY_INT_SRC_LINK_DOWN		((u16)0x0010)
390 #define PHY_INT_SRC_CLEAR_ALL		((u16)0xffff)
391 
392 #define PHY_INT_MASK			(30)
393 #define PHY_INT_MASK_ENERGY_ON		((u16)0x0080)
394 #define PHY_INT_MASK_ANEG_COMP		((u16)0x0040)
395 #define PHY_INT_MASK_REMOTE_FAULT	((u16)0x0020)
396 #define PHY_INT_MASK_LINK_DOWN		((u16)0x0010)
397 #define PHY_INT_MASK_DEFAULT		(PHY_INT_MASK_ANEG_COMP | \
398 					 PHY_INT_MASK_LINK_DOWN)
399 
400 #define PHY_SPECIAL			(31)
401 #define PHY_SPECIAL_SPD			((u16)0x001C)
402 #define PHY_SPECIAL_SPD_10HALF		((u16)0x0004)
403 #define PHY_SPECIAL_SPD_10FULL		((u16)0x0014)
404 #define PHY_SPECIAL_SPD_100HALF		((u16)0x0008)
405 #define PHY_SPECIAL_SPD_100FULL		((u16)0x0018)
406 
407 /* USB Vendor Requests */
408 #define USB_VENDOR_REQUEST_WRITE_REGISTER	0xA0
409 #define USB_VENDOR_REQUEST_READ_REGISTER	0xA1
410 #define USB_VENDOR_REQUEST_GET_STATS		0xA2
411 
412 /* Interrupt Endpoint status word bitfields */
413 #define INT_ENP_RDFO_INT		((u32)BIT(22))
414 #define INT_ENP_TXE_INT			((u32)BIT(21))
415 #define INT_ENP_TX_DIS_INT		((u32)BIT(19))
416 #define INT_ENP_RX_DIS_INT		((u32)BIT(18))
417 #define INT_ENP_PHY_INT			((u32)BIT(17))
418 #define INT_ENP_MAC_ERR_INT		((u32)BIT(15))
419 #define INT_ENP_RX_FIFO_DATA_INT	((u32)BIT(12))
420 
421 #endif /* _SMSC75XX_H */
422