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Searched refs:SCLK_PWRMGT_CNTL (Results 1 – 22 of 22) sorted by relevance

/drivers/gpu/drm/radeon/
Drv770_dpm.c134 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable()
136 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable()
137 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in rv770_gfx_clock_gating_enable()
138 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in rv770_gfx_clock_gating_enable()
173 if (RREG32(SCLK_PWRMGT_CNTL) & DYN_GFX_CLK_OFF_EN) in rv770_restore_cgcg()
177 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in rv770_restore_cgcg()
182 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in rv770_start_dpm()
200 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); in rv770_stop_dpm()
854 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); in rv770_program_tp()
856 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); in rv770_program_tp()
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Dcypress_dpm.c103 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
104 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
105 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
141 WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN); in cypress_gfx_clock_gating_enable()
143 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable()
145 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable()
146 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in cypress_gfx_clock_gating_enable()
147 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in cypress_gfx_clock_gating_enable()
151 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN); in cypress_gfx_clock_gating_enable()
248 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in cypress_enable_sclk_control()
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Dsumo_dpm.c92 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in sumo_gfx_clockgating_enable()
94 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in sumo_gfx_clockgating_enable()
95 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in sumo_gfx_clockgating_enable()
96 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in sumo_gfx_clockgating_enable()
442 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); in sumo_program_tp()
444 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); in sumo_program_tp()
447 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); in sumo_program_tp()
450 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); in sumo_program_tp()
918 WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET); in sumo_reset_am()
923 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET); in sumo_start_am()
Dr600_dpm.c245 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable()
247 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable()
304 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in r600_enable_sclk_control()
306 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); in r600_enable_sclk_control()
359 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); in r600_select_td()
361 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); in r600_select_td()
363 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); in r600_select_td()
365 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); in r600_select_td()
Dtrinity_dpm.c445 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in trinity_gfx_clockgating_enable()
447 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in trinity_gfx_clockgating_enable()
448 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in trinity_gfx_clockgating_enable()
449 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in trinity_gfx_clockgating_enable()
508 WREG32_P(SCLK_PWRMGT_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); in trinity_gfx_powergating_enable()
510 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_PWR_DOWN_EN); in trinity_gfx_powergating_enable()
772 if (RREG32(SCLK_PWRMGT_CNTL) & DYNAMIC_PM_EN) in trinity_wait_for_dpm_enabled()
803 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~(RESET_SCLK_CNT | RESET_BUSY_CNT)); in trinity_start_am()
808 WREG32_P(SCLK_PWRMGT_CNTL, RESET_SCLK_CNT | RESET_BUSY_CNT, in trinity_reset_am()
Drv730d.h83 #define SCLK_PWRMGT_CNTL 0x644 macro
Dtrinityd.h175 #define SCLK_PWRMGT_CNTL 0x678 macro
Drv730_dpm.c453 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in rv730_start_dpm()
471 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); in rv730_stop_dpm()
Dsumod.h152 #define SCLK_PWRMGT_CNTL 0x644 macro
Dci_dpm.c1540 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); in ci_start_dpm()
1542 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); in ci_start_dpm()
1601 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); in ci_stop_dpm()
1603 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); in ci_stop_dpm()
1624 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); in ci_enable_sclk_control()
1630 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); in ci_enable_sclk_control()
2043 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); in ci_program_vc()
2045 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); in ci_program_vc()
2061 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL); in ci_clear_vc()
2063 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); in ci_clear_vc()
Dkv_dpm.c660 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_start_am()
665 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); in kv_start_am()
670 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_reset_am()
674 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl); in kv_reset_am()
Drv770d.h158 #define SCLK_PWRMGT_CNTL 0x644 macro
Dnid.h599 #define SCLK_PWRMGT_CNTL 0x644 macro
Dsi_dpm.c3400 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in si_enable_sclk_control()
3402 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); in si_enable_sclk_control()
3832 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); in si_program_tp()
3834 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); in si_program_tp()
3837 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); in si_program_tp()
3840 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); in si_program_tp()
Dsid.h251 #define SCLK_PWRMGT_CNTL 0x788 macro
Dcikd.h111 #define SCLK_PWRMGT_CNTL 0xC0200008 macro
Dni_dpm.c1205 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
1206 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
1207 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
Devergreend.h137 #define SCLK_PWRMGT_CNTL 0x644 macro
Dr600d.h1307 #define SCLK_PWRMGT_CNTL 0x620 macro
/drivers/gpu/drm/amd/powerplay/hwmgr/
Dsmu7_hwmgr.c388 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); in smu7_program_voting_clients()
390 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); in smu7_program_voting_clients()
416 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1); in smu7_clear_voting_clients()
418 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1); in smu7_clear_voting_clients()
861 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, in smu7_enable_sclk_control()
984 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, in smu7_start_dpm()
1059 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, in smu7_stop_dpm()
/drivers/gpu/drm/amd/amdgpu/
Dsi_dpm.c3878 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in si_enable_sclk_control()
3880 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); in si_enable_sclk_control()
4316 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); in si_program_tp()
4318 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); in si_program_tp()
4321 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); in si_program_tp()
4324 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); in si_program_tp()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h253 #define SCLK_PWRMGT_CNTL 0x1e2 macro