Searched refs:SET (Results 1 – 15 of 15) sorted by relevance
| /drivers/gpu/drm/sti/ |
| D | sti_awg_utils.c | 15 SET, enumerator
67 opcode = SET; in awg_generate_instr()
95 case SET: in awg_generate_instr()
136 ret |= awg_generate_instr((timing->trailing_pixels > 0) ? SET : RPLSET, in awg_generate_line_signal()
146 ret |= awg_generate_instr(SET, val, 0, 0, fwparams); in awg_generate_line_signal()
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| /drivers/clk/imx/ |
| D | clk-pfd.c | 37 #define SET 0x4 macro
54 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + SET); in clk_pfd_disable()
106 writel_relaxed(frac << (pfd->idx * 8), pfd->reg + SET); in clk_pfd_set_rate()
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| /drivers/clk/mxs/ |
| D | clk-pll.c | 42 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
69 writel_relaxed(1 << 31, pll->base + SET); in clk_pll_disable()
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| D | clk-imx28.c | 80 writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET); in mxs_saif_clkmux_select()
90 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); in clk_misc_init()
93 writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET); in clk_misc_init()
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| D | clk-imx23.c | 55 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); in clk_misc_init()
76 writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET); in clk_misc_init()
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| D | clk.h | 20 #define SET 0x4 macro
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| D | clk-ref.c | 50 writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET); in clk_ref_disable()
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| /drivers/pwm/ |
| D | pwm-mxs.c | 24 #define SET 0x4 macro
110 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET); in mxs_pwm_enable()
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| /drivers/pinctrl/freescale/ |
| D | pinctrl-mxs.h | 18 #define SET 0x4 macro
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| D | pinctrl-mxs.c | 298 writel(1 << shift, reg + SET); in mxs_pinconf_group_set()
309 writel(1 << shift, reg + SET); in mxs_pinconf_group_set()
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| /drivers/mtd/nand/ |
| D | denali.h | 373 #define SET 1 /*use this to set a field instead of "pass"*/ macro
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| /drivers/scsi/ |
| D | 53c700.scr | 164 SET TARGET
239 SET ATN
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| D | 53c700_d.h_shipped | 200 SET TARGET
395 SET ATN
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| /drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| D | ctxnv50.c | 195 cp_set (ctx, UNK01, SET); in nv50_grctx_generate()
201 cp_bra (ctx, UNK0B, SET, cp_prepare_exit); in nv50_grctx_generate()
206 cp_set (ctx, UNK1D, SET); in nv50_grctx_generate()
210 cp_set (ctx, UNK01, SET); in nv50_grctx_generate()
215 cp_set (ctx, UNK03, SET); in nv50_grctx_generate()
225 cp_set (ctx, UNK20, SET); in nv50_grctx_generate()
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| /drivers/net/fddi/skfp/h/ |
| D | skfbi.h | 1037 #define SET(io,mask) outpw((io),inpw(io)|(mask)) macro
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