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Searched refs:SPLL_REF_DIV (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/radeon/
Drv740d.h30 #define SPLL_REF_DIV(x) ((x) << 4) macro
Drv730d.h31 #define SPLL_REF_DIV(x) ((x) << 4) macro
Drs780d.h29 # define SPLL_REF_DIV(x) ((x) << 2) macro
Drv740_dpm.c149 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv740_populate_sclk_value()
Drv730_dpm.c80 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv730_populate_sclk_value()
Drv770d.h94 #define SPLL_REF_DIV(x) ((x) << 4) macro
Dnid.h542 #define SPLL_REF_DIV(x) ((x) << 4) macro
Dsid.h89 #define SPLL_REF_DIV(x) ((x) << 4) macro
Dcikd.h254 #define SPLL_REF_DIV(x) ((x) << 5) macro
Devergreend.h78 #define SPLL_REF_DIV(x) ((x) << 4) macro
Dr600d.h1273 # define SPLL_REF_DIV(x) ((x) << 2) macro
Drv770_dpm.c527 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv770_populate_sclk_value()
Dni_dpm.c2028 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in ni_calculate_sclk_params()
Dsi_dpm.c4867 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in si_calculate_sclk_params()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h91 #define SPLL_REF_DIV(x) ((x) << 4) macro
/drivers/gpu/drm/amd/powerplay/smumgr/
Dfiji_smc.c652 SPLL_REF_DIV, dividers.uc_pll_ref_div); in fiji_calculate_sclk_params()
Diceland_smc.c669 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in iceland_calculate_sclk_params()
Dtonga_smc.c474 CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div); in tonga_calculate_sclk_params()
/drivers/gpu/drm/amd/amdgpu/
Dsi_dpm.c5347 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in si_calculate_sclk_params()