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Searched refs:SPLL_RESET (Results 1 – 19 of 19) sorted by relevance

/drivers/gpu/drm/radeon/
Drv740d.h27 #define SPLL_RESET (1 << 0) macro
Drv730d.h27 #define SPLL_RESET (1 << 0) macro
Drs780d.h27 # define SPLL_RESET (1 << 0) macro
Drv740_dpm.c369 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN; in rv740_populate_smc_acpi_state()
Drv730_dpm.c291 spll_func_cntl |= SPLL_RESET | SPLL_BYPASS_EN; in rv730_populate_smc_acpi_state()
Drv770d.h90 #define SPLL_RESET (1 << 0) macro
Dnid.h539 #define SPLL_RESET (1 << 0) macro
Dsid.h86 #define SPLL_RESET (1 << 0) macro
Dcikd.h251 #define SPLL_RESET (1 << 0) macro
Devergreend.h75 #define SPLL_RESET (1 << 0) macro
Dr600d.h1271 # define SPLL_RESET (1 << 0) macro
Dcypress_dpm.c1428 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN; in cypress_populate_smc_acpi_state()
Drv770_dpm.c977 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN; in rv770_populate_smc_acpi_state()
Dci_dpm.c3005 spll_func_cntl |= SPLL_RESET; in ci_populate_smc_acpi_level()
Dsi.c4015 tmp |= SPLL_RESET; in si_spll_powerdown()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h88 #define SPLL_RESET (1 << 0) macro
/drivers/gpu/drm/amd/powerplay/smumgr/
Dfiji_smc.c1135 SPLL_RESET, 1); in fiji_populate_smc_acpi_level()
Diceland_smc.c1336 CG_SPLL_FUNC_CNTL, SPLL_RESET, 1); in iceland_populate_smc_acpi_level()
Dtonga_smc.c1128 SPLL_RESET, 1); in tonga_populate_smc_acpi_level()