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Searched refs:SSPP_DMA0 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/msm/mdp/mdp5/
Dmdp5_cfg.c37 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
107 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
178 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
255 [SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
317 [SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
Dmdp5_ctl.c325 case SSPP_DMA0: return MDP5_CTL_LAYER_REG_DMA0(stage); in mdp_ctl_blend_mask()
346 case SSPP_DMA0: return MDP5_CTL_LAYER_EXT_REG_DMA0_BIT3; in mdp_ctl_blend_ext_mask()
421 case SSPP_DMA0: return MDP5_CTL_FLUSH_DMA0; in mdp_ctl_flush_mask_pipe()
Dmdp5_kms.c331 SSPP_DMA0, SSPP_DMA1, in modeset_init() enumerator
Dmdp5.xml.h66 SSPP_DMA0 = 6, enumerator
533 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]); in __offset_PIPE()