Searched refs:SSPP_VIG2 (Results 1 – 4 of 4) sorted by relevance
| /drivers/gpu/drm/msm/mdp/mdp5/ |
| D | mdp5_cfg.c | 36 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
106 [SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
177 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
316 [SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
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| D | mdp5_ctl.c | 321 case SSPP_VIG2: return MDP5_CTL_LAYER_REG_VIG2(stage); in mdp_ctl_blend_mask()
342 case SSPP_VIG2: return MDP5_CTL_LAYER_EXT_REG_VIG2_BIT3; in mdp_ctl_blend_ext_mask()
417 case SSPP_VIG2: return MDP5_CTL_FLUSH_VIG2; in mdp_ctl_flush_mask_pipe()
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| D | mdp5_kms.c | 328 SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3, in modeset_init() enumerator
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| D | mdp5.xml.h | 62 SSPP_VIG2 = 2, enumerator
529 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]); in __offset_PIPE()
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