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Searched refs:TIME_STAMP_INT_ENABLE (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/radeon/
Dcikd.h1339 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
1371 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Dradeon_kfd.c452 TIME_STAMP_INT_ENABLE | OPCODE_ERROR_INT_ENABLE); in kgd_init_interrupts()
Dnid.h497 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Dsid.h1282 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Devergreen.c4658 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4662 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4666 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4672 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
Devergreend.h1250 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Dcik.c7122 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7127 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7135 cp_m1p0 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7151 cp_m1p0 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
Dr600d.h718 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
Dsi.c6113 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6117 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6121 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
Dr600.c3826 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h1311 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
/drivers/gpu/drm/amd/amdgpu/
Dgfx_v8_0.c6405 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, in gfx_v8_0_set_gfx_eop_interrupt_state()
6432 WREG32_FIELD(CP_ME1_PIPE0_INT_CNTL, TIME_STAMP_INT_ENABLE, in gfx_v8_0_set_compute_eop_interrupt_state()