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Searched refs:TRAP_ENABLE (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsi_dma.c645 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
650 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
661 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
666 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
Dsdma_v2_4.c1111 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1116 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
1127 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1132 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
Dsdma_v3_0.c1373 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1378 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
1389 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1394 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
/drivers/gpu/drm/radeon/
Devergreen.c4559 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4563 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4652 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_irq_set()
4678 dma_cntl |= TRAP_ENABLE; in evergreen_irq_set()
4682 dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; in evergreen_irq_set()
4685 dma_cntl1 |= TRAP_ENABLE; in evergreen_irq_set()
Dnid.h1324 # define TRAP_ENABLE (1 << 0) macro
Dsi.c5949 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5951 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
6104 dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
6105 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
6125 dma_cntl |= TRAP_ENABLE; in si_irq_set()
6130 dma_cntl1 |= TRAP_ENABLE; in si_irq_set()
Dsid.h1834 # define TRAP_ENABLE (1 << 0) macro
Dcik.c6935 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
6937 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
7119 dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7120 dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7164 dma_cntl |= TRAP_ENABLE; in cik_irq_set()
7169 dma_cntl1 |= TRAP_ENABLE; in cik_irq_set()
Dcikd.h1963 # define TRAP_ENABLE (1 << 0) macro
Dr600.c3627 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_disable_interrupt_state()
3809 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_irq_set()
3831 dma_cntl |= TRAP_ENABLE; in r600_irq_set()
Devergreend.h1405 # define TRAP_ENABLE (1 << 0) macro
Dr600d.h632 # define TRAP_ENABLE (1 << 0) macro
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h1898 # define TRAP_ENABLE (1 << 0) macro