Searched refs:UPLL_FB_DIV (Results 1 – 9 of 9) sorted by relevance
/drivers/gpu/drm/radeon/ |
D | rv770.c | 78 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks() 85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); in rv770_set_uvd_clocks() 103 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), in rv770_set_uvd_clocks() 116 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); in rv770_set_uvd_clocks()
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D | rv770d.h | 62 # define UPLL_FB_DIV(x) ((x) << 0) macro
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D | sid.h | 146 # define UPLL_FB_DIV(x) ((x) << 0) macro
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D | evergreend.h | 367 # define UPLL_FB_DIV(x) ((x) << 0) macro
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D | r600d.h | 1561 # define UPLL_FB_DIV(x) ((x) << 4) macro
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D | r600.c | 251 UPLL_FB_DIV(fb_div) | in r600_set_uvd_clocks()
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D | evergreen.c | 1233 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in evergreen_set_uvd_clocks()
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D | si.c | 7463 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in si_set_uvd_clocks()
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/drivers/gpu/drm/amd/include/asic_reg/si/ |
D | sid.h | 148 # define UPLL_FB_DIV(x) ((x) << 0) macro
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