Home
last modified time | relevance | path

Searched refs:UPLL_FB_DIV (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/radeon/
Drv770.c78 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); in rv770_set_uvd_clocks()
103 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), in rv770_set_uvd_clocks()
116 WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1)); in rv770_set_uvd_clocks()
Drv770d.h62 # define UPLL_FB_DIV(x) ((x) << 0) macro
Dsid.h146 # define UPLL_FB_DIV(x) ((x) << 0) macro
Devergreend.h367 # define UPLL_FB_DIV(x) ((x) << 0) macro
Dr600d.h1561 # define UPLL_FB_DIV(x) ((x) << 4) macro
Dr600.c251 UPLL_FB_DIV(fb_div) | in r600_set_uvd_clocks()
Devergreen.c1233 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in evergreen_set_uvd_clocks()
Dsi.c7463 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in si_set_uvd_clocks()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h148 # define UPLL_FB_DIV(x) ((x) << 0) macro