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Searched refs:VC4_SET_FIELD (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/vc4/
Dvc4_plane.c410 VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) | in vc4_write_tpz()
411 VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE)); in vc4_write_tpz()
413 VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP)); in vc4_write_tpz()
422 VC4_SET_FIELD(scale, SCALER_PPF_SCALE) | in vc4_write_ppf()
423 VC4_SET_FIELD(0, SCALER_PPF_IPHASE)); in vc4_write_ppf()
549 VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) | in vc4_plane_mode_set()
550 VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1)); in vc4_plane_mode_set()
555 VC4_SET_FIELD(0xff, SCALER_POS0_FIXED_ALPHA) | in vc4_plane_mode_set()
556 VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) | in vc4_plane_mode_set()
557 VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y)); in vc4_plane_mode_set()
[all …]
Dvc4_crtc.c396 VC4_SET_FIELD((mode->htotal - in vc4_crtc_mode_set_nofb()
399 VC4_SET_FIELD((mode->hsync_end - in vc4_crtc_mode_set_nofb()
403 VC4_SET_FIELD((mode->hsync_start - in vc4_crtc_mode_set_nofb()
406 VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE)); in vc4_crtc_mode_set_nofb()
409 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, in vc4_crtc_mode_set_nofb()
411 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, in vc4_crtc_mode_set_nofb()
414 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, in vc4_crtc_mode_set_nofb()
416 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); in vc4_crtc_mode_set_nofb()
420 VC4_SET_FIELD(mode->crtc_vtotal - in vc4_crtc_mode_set_nofb()
423 VC4_SET_FIELD(mode->crtc_vsync_end - in vc4_crtc_mode_set_nofb()
[all …]
Dvc4_hdmi.c406 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, in vc4_hdmi_encoder_mode_set()
408 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, in vc4_hdmi_encoder_mode_set()
410 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); in vc4_hdmi_encoder_mode_set()
411 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | in vc4_hdmi_encoder_mode_set()
412 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, in vc4_hdmi_encoder_mode_set()
414 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | in vc4_hdmi_encoder_mode_set()
415 VC4_SET_FIELD(mode->crtc_vtotal - in vc4_hdmi_encoder_mode_set()
439 VC4_SET_FIELD(mode->hdisplay * pixel_rep, in vc4_hdmi_encoder_mode_set()
443 VC4_SET_FIELD((mode->htotal - in vc4_hdmi_encoder_mode_set()
446 VC4_SET_FIELD((mode->hsync_end - in vc4_hdmi_encoder_mode_set()
[all …]
Dvc4_dpi.c289 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
293 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, in vc4_dpi_encoder_enable()
295 dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER); in vc4_dpi_encoder_enable()
298 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2, in vc4_dpi_encoder_enable()
302 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, in vc4_dpi_encoder_enable()
306 dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3, in vc4_dpi_encoder_enable()
Dvc4_gem.c401 VC4_SET_FIELD(0xf, V3D_SLCACTL_T1CC) | in vc4_flush_caches()
402 VC4_SET_FIELD(0xf, V3D_SLCACTL_T0CC) | in vc4_flush_caches()
403 VC4_SET_FIELD(0xf, V3D_SLCACTL_UCC) | in vc4_flush_caches()
404 VC4_SET_FIELD(0xf, V3D_SLCACTL_ICC)); in vc4_flush_caches()
Dvc4_validate.c384 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32, in validate_tile_binning_config()
386 VC4_SET_FIELD(VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128, in validate_tile_binning_config()
Dvc4_regs.h16 #define VC4_SET_FIELD(value, field) \ macro
Dvc4_render_cl.c80 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE, in vc4_store_before_load()