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Searched refs:VCLK_SRC_SEL_MASK (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/radeon/
Drv770.c59 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in rv770_set_uvd_clocks()
125 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in rv770_set_uvd_clocks()
Drv770d.h58 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
Dsid.h142 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
Devergreend.h363 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
Dr600d.h1577 # define VCLK_SRC_SEL_MASK 0x01F00000 macro
Dr600.c205 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in r600_set_uvd_clocks()
283 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in r600_set_uvd_clocks()
Devergreen.c1193 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in evergreen_set_uvd_clocks()
1266 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in evergreen_set_uvd_clocks()
Dsi.c7422 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in si_set_uvd_clocks()
7496 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK)); in si_set_uvd_clocks()
/drivers/video/fbdev/aty/
Dradeon_base.c1391 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); in radeon_write_pll_regs()
1451 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); in radeon_write_pll_regs()
/drivers/gpu/drm/amd/include/asic_reg/si/
Dsid.h144 # define VCLK_SRC_SEL_MASK 0x01F00000 macro